Sr. Manager DFT

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up and spec to the product. With 3200 employees worldwide Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities including its advanced silicon and system testing labs.

Tessolve offers a Turnkey ASIC Solution from design to packaged parts. Tessolves design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA IP and foundries. Our front-end design strengths integrated with the knowledge from the backend flow allows Tessolve to catch design flaws ahead in the cycle thus reducing expensive re-design costs and risks. We actively invest in the R&D center of excellence initiatives such as 5G mmWave Silicon photonics HSIO HBM/HPI system-level test and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Avionics Automotive Industrial and Medical segments. Tessolves Embedded Engineering services enable customers a faster time-to-market through deep domain expertise innovative ideas diverse embedded hardware & software services and built-in infrastructure with world-class lab facilities.

Tessolves clientele includes Tier 1 clients across multiple market segments 9 of the top 10 semiconductor companies start-ups and government entities. We have a global presence over 12 countries with office locations in the United States India Singapore Malaysia Germany United Kingdom Canada UK Japan Taiwan Philippines and Test Labs in India Singapore Malaysia Austin San Jose.

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Join our innovative team as a Design-for-Test Manager in Bangalore where youll lead efforts to deliver exceptional DFT solutions for complex SoC and ASIC projects. Collaborate across various engineering teams to enhance methodologies and integrate cutting-edge DFT features. Your leadership will drive project success and customer satisfaction in a dynamic global technology landscape.

Job Designation: Design-for-Test (DFT) Manager

Years of Exp : 10

Job Location: Bangalore

Lead the DFT team to deliver solutions across multiple ASIC projects.

Oversee DFT architecture planning and verification processes.

Collaborate with cross-functional teams to ensure smooth DFT integration.

Review and optimize ATPG/MBIST/LBIST strategies.

Initiate and drive methodology enhancements and automation.

Manage project schedules deliverables and resources.

Provide guidance mentoring and feedback to team members.

Engage with clients on technical discussions and updates.

Support post-silicon bring-up and pattern debug as needed.

Expert in scan insertion ATPG MBIST and test-mode integration.

Experienced with industry-standard DFT/ATPG tools like Synopsys Cadence.

Proficient in RTL design CDC synthesis and physical design flows.

Proven leader in managing complex DFT programs.

Strong problem-solving and communication skills.

Background in silicon bring-up and production test is advantageous.

Holds a degree in Electronics Electrical VLSI or a related field.

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