Senior Staff Engineer, Physical Verification

We are seeking an experienced Physical Verification (PV) Engineer to drive signoff verification and tapeout readiness for advanced ASIC/SoC designs. The candidate will be responsible for executing and debugging physical verification checks driving violation closure maintaining foundry-qualified verification flows and ensuring block and full-chip layouts meet manufacturing requirements before tapeout.

Key Responsibilities

• Perform and drive signoff Physical Verification for block- and chip-level designs.
• Execute and analyze DRC LVS ERC Antenna and Density checks using industry-standard signoff tools.
• Debug verification violations and provide actionable recommendations to Physical Design and Layout teams.
• Drive closure of signoff issues through effective tracking prioritization and cross-functional collaboration.
• Maintain and support foundry-qualified rule decks runsets and waiver management processes.
• Manage waiver tracking and ensure compliance with foundry guidelines and project signoff requirements.
• Coordinate verification re-runs following design changes and ECOs to identify regressions and maintain signoff quality.
• Work closely with Physical Design Layout Foundry/PDK and Program teams to achieve tapeout milestones.
• Generate periodic signoff status reports metrics and violation summaries for project reviews.
• Prepare final signoff evidence including DRC/LVS-clean reports waiver summaries and residual risk assessments for tapeout reviews.

Qualifications :

• Bachelors or Masters degree in Electronics Engineering or Electrical Engineering.
• 10-15 years of experience in Physical Verification Physical Design or Backend Implementation.
• Strong expertise in DRC LVS ERC Antenna and Density verification methodologies.
• Hands-on experience with Calibre Pegasus or equivalent physical verification tools.
• Good understanding of foundry signoff requirements PDKs and semiconductor manufacturing rules.
• Experience in debugging and resolving complex signoff violations at block and full-chip levels.
• Familiarity with GDSII/OASIS databases netlists and tapeout processes.
• Proficiency in Tcl Python Perl or Shell scripting.

Preferred Qualifications

• Experience with advanced technology nodes (7nm 5nm 3nm and below).
• Knowledge of Physical Design PDN STA and implementation flows.
• Experience supporting multiple successful SoC tapeouts.
• Strong problem-solving communication and stakeholder management skills.

Why Join Us

Join a high-impact team responsible for ensuring silicon manufacturability and signoff quality for next-generation SoCs. You will work closely with design implementation and foundry teams to drive successful tapeouts on cutting-edge process technologies.

Additional Information :

Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. With a global team of over 21000 engineers and problem solvers in more than 30 countries we offer the opportunity to work on worldleading technology for Automotive Industrial Infrastructure and IoT shaping a safer healthier greener and smarter future.

At Renesas TAGIE is our culture grounded in being Transparent Agile Global Innovative and Entrepreneurial. It shapes how we work grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us

Renesas Electronics is an equal opportunity and affirmative action employer committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex race religion national origin gender gender identity gender expression age sexual orientation military status veteran status or any other basis protected by law. For more information please read our Diversity & Inclusion Statement.

Remote Work :

No

Employment Type :

Full-time