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Principle DFT Engineer
Job Location:
Monthly Salary:
Posted:
3 July 2026 (30+ days ago)
Posted:
Application Deadline:
30 September 2026
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
We are seeking an experienced DFT Engineer (712 years) with strong hands-on expertise in Scan Insertion ATPG and Gate-Level Simulation (GLS) for complex SoC designs. The candidate will be responsible for implementing and verifying scan architectures performing scan insertion generating and analyzing ATPG patterns for stuck-at and transition faults and executing GLS with and without SDF for DFT validation. The role requires close collaboration with RTL physical design and test teams to ensure high fault coverage clean DFT signoff and timely tape-out support. Proficiency with industry-standard DFT tools (Mentor/Siemens Tessent Synopsys or Cadence) solid Verilog/SystemVerilog skills and the ability to debug DFT and GLS issues independently are essential. Prior experience supporting pre- and post-silicon activities is a plus.
#LI-9415Required Experience:
IC
About Company
NXP is a global semiconductor company creating solutions that enable secure connections for a smarter world.
