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PRINCIPAL ANALOG MIXED SIGNAL ENGINEER

Vrinda International

Job Location:

Bengaluru - India

Monthly Salary: L 19 - 19

Experience Required: 12-18years

Posted: 2 September 2026 (9 days ago)

Application Deadline: 30 November 2026

Vacancies: 1 Vacancy

Job Summary

HIRING PRINCIPAL ANALOG MIXED SIGNAL ENGINEER

Location: Trivandrum Bangalore Chennai

Experience: 1218 Years

CTC: Up to 19 LPA

Work Mode: Work From Office (WFO)

ROLE OVERVIEW

We are looking for an experienced Principal Analog Mixed Signal Engineer to lead end-to-end ASIC/SoC Analog & Mixed-Signal IP development from architecture and circuit design to tape-out silicon bring-up characterization and production support.

KEY RESPONSIBILITIES

Own AMS IP/subsystem development from concept to production

Define architecture roadmap and technical strategy

Lead design reviews and mentor AMS teams

Drive verification sign-off tape-out and silicon validation

Support characterization yield improvement and productization

Collaborate with Digital Physical Design Verification Packaging & Test teams

Interface with customers on technical requirements and solutions MUST-HAVE SKILLS

PLL/DLL ADC/DAC Bandgap LDO & Power Management

Oscillators Comparators Charge Pumps & Sensor Interfaces

Cadence Virtuoso Spectre/APS ADE XL/Explorer/Assembler

HSPICE & AMS Verification

Verilog-A / Verilog-AMS

PVT Monte Carlo mismatch noise & reliability analysis

DRC LVS ERC PEX & post-layout simulation

Multiple successful silicon tape-outs

Silicon bring-up & characterization experience

PREFERRED SKILLS

FinFET technology exposure

SerDes experience

MIPI experience

USB experience

PCIe experience

DDR PHY experience

ISO 26262 / IEC 61508 exposure

Low-power analog design techniques

Python / Perl / TCL scripting

Productization & yield improvement experience

Qualification: B.E./ in Electronics Electrical VLSI Microelectronics or related field.

Required Skills:

MUST-HAVE SKILLS PLL/DLL ADC/DAC Bandgap LDO & Power Management Oscillators Comparators Charge Pumps & Sensor Interfaces Cadence Virtuoso Spectre/APS ADE XL/Explorer/Assembler HSPICE & AMS Verification Verilog-A / Verilog-AMS PVT Monte Carlo mismatch noise & reliability analysis DRC LVS ERC PEX & post-layout simulation Multiple successful silicon tape-outs Silicon bring-up & characterization experience PREFERRED SKILLS FinFET technology exposure SerDes experience MIPI experience USB experience PCIe experience DDR PHY experience ISO 26262 / IEC 61508 exposure Low-power analog design techniques Python / Perl / TCL scripting Productization & yield improvement experience

Required Education:

Bachelors Degree (MBA Preferred)

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