Member of Technical Staff Design Verification & Validation

Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads and enable a new era of domain-specific chips that unlock capabilities impossible with current hardware paradigms. Born out of Stanford Research our team blends AI with Silicon with a founding team from Anthropic Google DeepMind Meta SuperIntelligence xAI Apple and Intel.

As a Founding Member of the Technical Staff on the Design Verification team at Architect youll own the verification strategy behind AI-generated designs taping out on leading foundries. Youll work at the intersection of rigorous hardware verification and AI-driven design automation.

• Review AI-driven test plan and validation strategy for internal and external SoC projects.

• Provide domain-specific expertise to our AI/ML teams including architectural and microarchitectural checks validation modularity checkers coverage models and interface protocols helping encode DV best practices into our AI-driven flows.

• Independently define drive and coordinate validation verification and integration flows across multiple IPs including checkpoints and collateral handoffs.

• Collaborate with architecture design and AI/ML leads to generate simulation- and emulation-ready collateral that scales across projects.

• Track emerging trends in semiconductor verification and AI-driven design automation to keep our methodology cutting-edge in quality scalability and throughput.

Qualifications & Skills:

• Degree: Bachelors Masters or PhD in Electrical Engineering Computer Engineering or a closely related field.

• Tapeout Experience: 5 years (10 preferred) working on advanced-node tapeouts at top chip companies or fast-moving silicon startups. End-to-end silicon delivery is a strong plus.

• Verification Expertise: Deep expertise in verification/validation emulation and architectural and system-level verification of industry-standard IPs. Proven track record defining microarchitectural checkers and monitors modeling IP and SoC validation platforms and developing modular reusable validation collateral.

• Coding: Strong skills in SystemVerilog UVM and C/C for test environments. Python strongly preferred.

• Subsystem Depth: Hands-on verification experience in at least one of the following areas:

  • ARM/AMBA protocols (APB AHB AXI and ideally ACE for coherent CPU interfaces)

  • CPU subsystems boot interrupts debug coherency

  • Memory controllers and PHY LPDDR/DDR interfaces controller-level verification

  • On-chip interconnect / NoC routing arbitration QoS bandwidth

  • NPU / ML accelerator cores datapath scratchpad memory DMA engines

  • Security IPs and/or working with secure enclaves

• Methodology: Hands-on experience with simulation and emulation flows and methodologies. Experience mapping IP and SoC designs to FPGA prototypes for fast functional verification.

• Execution: Excellent problem-solving collaboration and communication skills with strong attention to detail. Ability to work independently and drive cross-functional alignment.

• Leadership: Ability and desire to lead the DV function over time as the team scales.

Bonus:

• SoC-level DV experience bringing up full systems with memory controller PHY CPU connectivity validating top-level integration.

• Deep experience with AMBA protocols specifically ACE for coherent CPU-memory access.

• FPGA prototyping experience (ideally Xilinx Vivado/Vitis).

• Verification experience spanning multiple of: interconnects CPU subsystems ARM AMBA memory controllers NPUs.

• Tapeout experience at frontier AI chip startups (MatX Groq Cerebras d-Matrix etc.) or tier-1 silicon companies (Apple NVIDIA Google Qualcomm Broadcom AMD).

• Competitive salary and meaningful equity stake

• Fast-paced startup with autonomy and visible impact

• Cutting-edge challenges at the intersection of AI and silicon design

Required Experience:

Staff IC