Prototyping Design Software Engineer

Snap Inc is a technology company. We believe the camera presents the greatest opportunity to improve the way people live and communicate. Snap contributes to human progress by empowering people to express themselves live in the moment learn about the world and have fun together. The Companys three core products are Snapchat a visual messaging app that enhances your relationships with friends family and the world; Lens Studio an augmented reality platform that powers AR across Snapchat and other services; and its AR glasses Spectacles.

Specs Inc. is a wholly-owned subsidiary of Snap Inc. dedicated to making computing more human. The company develops Specs advanced eyewear that seamlessly integrates digital experiences into the physical world.

Specs Inc. also provides Lens Studio a full suite of advanced developer tools that powers immersive augmented reality experiences across Specs Snapchat and other services.

We are looking for a Prototyping Design Engineer with strong SoC prototyping experience and enough embedded software skills to help bring platforms to life early. You will port complex SoC RTL onto FPGA HAPS and ZeBu platforms enable boot and software validation flows and collaborate across RTL verification system software and infrastructure teams. This role is ideal for someone who can move between hardware integration platform bring-up low-level software debug and RTOS/bare-metal enablement.

What youll do:

Port SoC and subsystem RTL onto FPGA HAPS and ZeBu platforms while keeping the prototyping code as close as possible to ASIC RTL and carefully managing target-specific conditionals.

Build and maintain pre-silicon platforms that enable early firmware software development bootloader/FSBL bring-up and validation of key interfaces such as eMMC LPDDR PCIe MIPI CSI2/DSI UART QSPI Flash SPI I2C/I3C GPIO and JTAG.

Rework RTL wrappers and platform-specific logic for prototyping targets including HAPS/ZeBu-specific interface PHY changes and controller-presence handling to support common software flows across SoC ZeBu HAPS and FPGA platforms.

Develop integrate or adapt low-level embedded software needed for bring-up including board support code boot configuration device drivers diagnostics and RTOS or bare-metal test applications.

Debug complex hardware/software bring-up issues across HAPS ZeBu and FPGA targets including memory-model integration reset and clock sequencing controller/PHY interaction timing issues waveform analysis JTAG/SWD debug and timing-report review.

Participate in designing developing and maintaining SoC validation tests at pre-tapeout stages using firmware bare-metal tests RTOS-based applications and host automation.

Partner with SoC verification infrastructure and external vendors to root-cause issues and accelerate pre-silicon software readiness.

Integrate prototyping platforms into CI/CD flows and improve build reliability automated regressions artifact traceability and shared platform infrastructure.

Knowledge Skills & Abilities:

Strong understanding of SoC RTL integration and the tradeoffs required to map large designs onto prototyping and emulation platforms.

Hands-on experience with FPGA prototyping and hardware emulation platforms such as HAPS ZeBu or similar Cadence/Siemens/Synopsys environments.

Experience with Static timing analysis for XILINX/Intel FPGA platforms

Proficiency in embedded C/C and ability to read write and debug low-level firmware for boot diagnostics drivers and hardware validation.

Experience with RTOS concepts and development including task/thread scheduling interrupts synchronization timers memory management device-driver integration and real-time constraints.

Experience with bare-metal development and boot flows including boot ROM/FSBL startup code linker scripts memory maps MMU/MPU/cache configuration and board support packages.

Familiarity with ARM Cortex-M/R/A architectures SoC peripherals and system interfaces such as LPDDR/DFI eMMC PCIe JTAG/SWD UART SPI I2C/I3C GPIO and QSPI Flash.

Experience debugging clocks resets timing issues waveforms platform bring-up problems and embedded software crashes or asserts across multiple pre-silicon targets.

Familiarity with debugging tools such as JTAG/SWD GDB trace logic analyzers waveform viewers embedded logging and diagnostic frameworks.

Ability to work from RTL hardware schematics datasheets and timing reports and to communicate platform limitations and integration constraints clearly across hardware and software teams.

Strong problem-solving communication teamwork and prioritization skills in a fast-paced cross-functional environment.

Minimum Qualifications:

Masters degree in Electrical Engineering Computer Engineering Computer Science or related field.

5 years of experience in SoC prototyping FPGA/emulation bring-up embedded software firmware or pre-silicon validation.

Experience with RTL integration FPGA prototyping hardware emulation or pre-silicon validation.

Demonstrated experience in C/C programming for embedded bare-metal or RTOS-based systems.

Experience bringing up complex SoC or subsystem designs on non-silicon targets and debugging boot firmware RTOS and hardware/software interface issues using waveforms JTAG/SWD logs and trace.

Preferred Qualifications:

Experience with Synopsys ZeBu and Synopsys HAPS platforms; experience with other Cadence Siemens or Synopsys emulation/prototyping environments is a plus.

Experience running embedded software diagnostics or RTOS-based applications on FPGA or emulator platforms.

Experience with RTOS platforms such as FreeRTOS Zephyr ThreadX QNX or similar including BSP/device-driver integration and real-time profiling.

Experience with ARM Cortex-M/R/A architectures bootloader/FSBL development memory subsystems such as LPDDR/DFI and storage or high-speed interfaces such as eMMC and PCIe.

Experience building or maintaining CI/CD pipelines for hardware prototyping and embedded software flows such as GitLab or TeamCity.

Experience working closely with system software teams on early boot FSBL driver RTOS and validation enablement.

If you have a disability or special need that requires accommodation please dont be shy and provide us some information.

Default Together Policy at Snap: At Snap Inc. we believe that being together in person helps us build our culture faster reinforce our values and serve our community customers and partners better through dynamic collaboration. To reflect this we practice a default together approach and expect our team members to work in an office 4 days per week.

At Snap we believe that having a team of diverse backgrounds and voices working together will enable us to create innovative products that improve the way people live and communicate. Snap is proud to be an equal opportunity employer and committed to providing employment opportunities regardless of race religious creed color national origin ancestry physical disability mental disability medical condition genetic information marital status sex gender gender identity gender expression pregnancy childbirth and breastfeeding age sexual orientation military or veteran status or any other protected classification in accordance with applicable federal state and local laws. EOE including disability/vets.

Our Benefits: Snap Inc. is its own community so weve got your back! We do our best to make sure you and your loved ones have everything you need to be happy and healthy on your own terms. Our benefits are built around your needs and include paid parental leave comprehensive medical coverage emotional and mental health support programs and compensation packages that let you share in Snaps long-term success!