Chelsea Search Group

Principal Digital Signal Processing (DSP) EngineerKey Responsibilities: Developing new DSP algorithms to be used in optical transceivers. Documenting design details and collaborating with ASIC firmware and verification teams to reliably transfer the design to ASIC products. Implementi

Principal Digital Signal Processing (DSP) EngineerKey Responsibilities: Developing new DSP algorithms to be used in optical transceivers. Documenting design details and collaborating with ASIC firmware and verification teams to reliably transfer the design to ASIC products. Implementi

Senior or Principal ASIC Design EngineerKey Responsibilities: Design and implement digital circuits using HDL (Verilog/ System Verilog) Perform synthesis timing analysis Lint formal equivalence Clock Domain Crossing (CDC) analysis Optimize designs for performance power and area (PPA)

Senior or Principal ASIC Design EngineerKey Responsibilities: Design and implement digital circuits using HDL (Verilog/ System Verilog) Perform synthesis timing analysis Lint formal equivalence Clock Domain Crossing (CDC) analysis Optimize designs for performance power and area (PPA)

Senior or Principal ASIC Design EngineerKey Responsibilities: Design and implement digital circuits using HDL (Verilog/ System Verilog) Perform synthesis timing analysis Lint formal equivalence Clock Domain Crossing (CDC) analysis Optimize designs for performance power and area (PPA)

Senior or Principal ASIC Design EngineerKey Responsibilities: Design and implement digital circuits using HDL (Verilog/ System Verilog) Perform synthesis timing analysis Lint formal equivalence Clock Domain Crossing (CDC) analysis Optimize designs for performance power and area (PPA)

Principal Digital Signal Processing (DSP) EngineerKey Responsibilities: Developing new DSP algorithms to be used in optical transceivers. Documenting design details and collaborating with ASIC firmware and verification teams to reliably transfer the design to ASIC products. Implementi

Principal Digital Signal Processing (DSP) EngineerKey Responsibilities: Developing new DSP algorithms to be used in optical transceivers. Documenting design details and collaborating with ASIC firmware and verification teams to reliably transfer the design to ASIC products. Implementi

Senior or Principal ASIC Design EngineerKey Responsibilities: Design and implement digital circuits using HDL (Verilog/ System Verilog) Perform synthesis timing analysis Lint formal equivalence Clock Domain Crossing (CDC) analysis Optimize designs for performance power and area (PPA)

Senior or Principal ASIC Design EngineerKey Responsibilities: Design and implement digital circuits using HDL (Verilog/ System Verilog) Perform synthesis timing analysis Lint formal equivalence Clock Domain Crossing (CDC) analysis Optimize designs for performance power and area (PPA)

Principal Digital Signal Processing (DSP) EngineerKey Responsibilities: Developing new DSP algorithms to be used in optical transceivers. Documenting design details and collaborating with ASIC firmware and verification teams to reliably transfer the design to ASIC products. Implementi

Principal Digital Signal Processing (DSP) EngineerKey Responsibilities: Developing new DSP algorithms to be used in optical transceivers. Documenting design details and collaborating with ASIC firmware and verification teams to reliably transfer the design to ASIC products. Implementi

Senior or Principal ASIC Design EngineerKey Responsibilities: Design and implement digital circuits using HDL (Verilog/ System Verilog) Perform synthesis timing analysis Lint formal equivalence Clock Domain Crossing (CDC) analysis Optimize designs for performance power and area (PPA)

Senior or Principal ASIC Design EngineerKey Responsibilities: Design and implement digital circuits using HDL (Verilog/ System Verilog) Perform synthesis timing analysis Lint formal equivalence Clock Domain Crossing (CDC) analysis Optimize designs for performance power and area (PPA)

Principal Static Timing Analysis (STA) EngineerAbout the Role:We are seeking a highly experienced Principal STA Engineer to play a key technical leadership role in the development of next-generation semiconductor this role you will own complex blocks and full-chip STA analysis and ac

Principal Static Timing Analysis (STA) EngineerAbout the Role:We are seeking a highly experienced Principal STA Engineer to play a key technical leadership role in the development of next-generation semiconductor this role you will own complex blocks and full-chip STA analysis and ac

Principal Static Timing Analysis (STA) EngineerAbout the Role:We are seeking a highly experienced Principal STA Engineer to play a key technical leadership role in the development of next-generation semiconductor this role you will own complex blocks and full-chip STA analysis and ac

Principal Static Timing Analysis (STA) EngineerAbout the Role:We are seeking a highly experienced Principal STA Engineer to play a key technical leadership role in the development of next-generation semiconductor this role you will own complex blocks and full-chip STA analysis and ac

Principal Physical Verification EngineerAbout the Role:We are seeking a Principal Physical Verification Engineering to be part of the Physical Design team delivering complex digital blocks and full-chip implementations in advanced process nodes. This role owns execution of all aspects

Principal Physical Verification EngineerAbout the Role:We are seeking a Principal Physical Verification Engineering to be part of the Physical Design team delivering complex digital blocks and full-chip implementations in advanced process nodes. This role owns execution of all aspects

Principal Physical Verification EngineerAbout the Role:We are seeking a Principal Physical Verification Engineering to be part of the Physical Design team delivering complex digital blocks and full-chip implementations in advanced process nodes. This role owns execution of all aspects

Principal Physical Verification EngineerAbout the Role:We are seeking a Principal Physical Verification Engineering to be part of the Physical Design team delivering complex digital blocks and full-chip implementations in advanced process nodes. This role owns execution of all aspects

Principal Physical Verification EngineerAbout the Role:We are seeking a Principal Physical Verification Engineering to be part of the Physical Design team delivering complex digital blocks and full-chip implementations in advanced process nodes. This role owns execution of all aspects

Principal Physical Verification EngineerAbout the Role:We are seeking a Principal Physical Verification Engineering to be part of the Physical Design team delivering complex digital blocks and full-chip implementations in advanced process nodes. This role owns execution of all aspects

Principal Static Timing Analysis (STA) EngineerAbout the Role:We are seeking a highly experienced Principal STA Engineer to play a key technical leadership role in the development of next-generation semiconductor this role you will own complex blocks and full-chip STA analysis and ac

Principal Static Timing Analysis (STA) EngineerAbout the Role:We are seeking a highly experienced Principal STA Engineer to play a key technical leadership role in the development of next-generation semiconductor this role you will own complex blocks and full-chip STA analysis and ac

Staff or Principal Analog Design EngineerUS Citizen or US Permanent Resident preferredFull-time Employee Bonus Benefits 401k Stock OptionsDuties & Responsibilities: Clock generation and distribution (VCOs PLL clock distribution etc) Design of custom passive components from concept to

Staff or Principal Analog Design EngineerUS Citizen or US Permanent Resident preferredFull-time Employee Bonus Benefits 401k Stock OptionsDuties & Responsibilities: Clock generation and distribution (VCOs PLL clock distribution etc) Design of custom passive components from concept to

Staff or Principal Analog Design EngineerUS Citizen or US Permanent Resident preferredFull-time Employee Bonus Benefits 401k Stock OptionsDuties & Responsibilities: Clock generation and distribution (VCOs PLL clock distribution etc) Design of custom passive components from concept to

Staff or Principal Analog Design EngineerUS Citizen or US Permanent Resident preferredFull-time Employee Bonus Benefits 401k Stock OptionsDuties & Responsibilities: Clock generation and distribution (VCOs PLL clock distribution etc) Design of custom passive components from concept to

Staff or Principal Analog Design EngineerUS Citizen or US Permanent Resident preferredFull-time Employee Bonus Benefits 401k Stock OptionsDuties & Responsibilities: Clock generation and distribution (VCOs PLL clock distribution etc) Design of custom passive components from concept to

Staff or Principal Analog Design EngineerUS Citizen or US Permanent Resident preferredFull-time Employee Bonus Benefits 401k Stock OptionsDuties & Responsibilities: Clock generation and distribution (VCOs PLL clock distribution etc) Design of custom passive components from concept to

Staff or Principal Analog Design EngineerUS Citizen or US Permanent Resident preferredFull-time Employee Bonus Benefits 401k Stock OptionsDuties & Responsibilities: Clock generation and distribution (VCOs PLL clock distribution etc) Design of custom passive components from concept to

Staff or Principal Analog Design EngineerUS Citizen or US Permanent Resident preferredFull-time Employee Bonus Benefits 401k Stock OptionsDuties & Responsibilities: Clock generation and distribution (VCOs PLL clock distribution etc) Design of custom passive components from concept to

Principal Physical Verification EngineerAbout the Role:We are seeking a Principal Physical Verification Engineering to be part of the Physical Design team delivering complex digital blocks and full-chip implementations in advanced process nodes. This role owns execution of all aspects

Principal Physical Verification EngineerAbout the Role:We are seeking a Principal Physical Verification Engineering to be part of the Physical Design team delivering complex digital blocks and full-chip implementations in advanced process nodes. This role owns execution of all aspects

Principal Physical Verification EngineerAbout the Role:We are seeking a Principal Physical Verification Engineering to be part of the Physical Design team delivering complex digital blocks and full-chip implementations in advanced process nodes. This role owns execution of all aspects

Principal Physical Verification EngineerAbout the Role:We are seeking a Principal Physical Verification Engineering to be part of the Physical Design team delivering complex digital blocks and full-chip implementations in advanced process nodes. This role owns execution of all aspects

Staff or Principal Analog Design EngineerUS Citizen or US Permanent Resident preferredFull-time Employee Bonus Benefits 401k Stock OptionsDuties & Responsibilities: Clock generation and distribution (VCOs PLL clock distribution etc) Design of custom passive components from concept to

Staff or Principal Analog Design EngineerUS Citizen or US Permanent Resident preferredFull-time Employee Bonus Benefits 401k Stock OptionsDuties & Responsibilities: Clock generation and distribution (VCOs PLL clock distribution etc) Design of custom passive components from concept to