FPGA Digital Design Engineering Intern (January 2027) (4-16 months)

Maintain and add new functionality to our FPGA code base including code to control and test our SDR (software-defined radio) and SDN (software-defined network);

Design custom IP for new features of both Keplers satellites and ground stations;

Add support for new sensors/communication interfaces (such as SPI I2C UART);

Work with high-speed FPGA interfaces (e.g. JESD204b 10G Ethernet Aurora).

2 years in an Electrical or Computer Engineering degree program or equivalent;

Experience with Verilog SystemVerilog or VHDL. (You will be working in SystemVerilog).

Currently enrolled in an undergraduate program at a Canadian post-secondary institution and returning to studies after the internship;

Available for a full-time 416 month internship beginning January 2027;

We have a strong preference for candidates who can work from our Toronto office at least 23 days per week to support collaboration and team engagement. We recognize that exceptional candidates may require a different arrangement and are open to discussing flexibility where appropriate.

Experience with DSP (digital signal processing) algorithms;

Strong skills with C and embedded programming;

Strong scripting experience (e.g. bash Python Tcl etc.);

Relevant experience through hobbies or a university design team.