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Design Verification Engineer
Job Location:
Monthly Salary:
Posted:
5 September 2026 (7 hours ago)
Posted:
Application Deadline:
3 December 2026
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Job Title: Design Verification Engineer
Client: NeurealM/ Microchip
Location: Vancouver BC Canada - Initial 1 month Hybrid then after Remote
Job Type: Contract
Job Summary
We are looking for aDesign Verification Engineerwith strong experience inASIC/SoC verificationto develop and execute verification environments and ensure high-quality digital designs.
Responsibilities
Develop verification environments and testbenches usingSystemVerilog and UVM.
Create and execute functional regression and constrained-random tests.
Analyzefunctional/code coverageand drive coverage closure.
Debug RTL and simulation failures and work with design teams to resolve issues.
Verify protocols such asAMBA/AXI PCIe Ethernet or similar interfaces.
Automate testing and regression usingPython Perl or Shell scripting.
Required Skills
StrongSystemVerilog & UVMexperience.
Solid understanding ofRTL digital design and ASIC/SoC verification.
Experience with simulation tools such asVCS Xcelium or Questa.
Strong debugging and scripting skills.
Bachelors/Masters degree inElectrical Electronics or Computer Engineering.
Client: NeurealM/ Microchip
Location: Vancouver BC Canada - Initial 1 month Hybrid then after Remote
Job Type: Contract
Job Summary
We are looking for aDesign Verification Engineerwith strong experience inASIC/SoC verificationto develop and execute verification environments and ensure high-quality digital designs.
Responsibilities
Develop verification environments and testbenches usingSystemVerilog and UVM.
Create and execute functional regression and constrained-random tests.
Analyzefunctional/code coverageand drive coverage closure.
Debug RTL and simulation failures and work with design teams to resolve issues.
Verify protocols such asAMBA/AXI PCIe Ethernet or similar interfaces.
Automate testing and regression usingPython Perl or Shell scripting.
Required Skills
StrongSystemVerilog & UVMexperience.
Solid understanding ofRTL digital design and ASIC/SoC verification.
Experience with simulation tools such asVCS Xcelium or Questa.
Strong debugging and scripting skills.
Bachelors/Masters degree inElectrical Electronics or Computer Engineering.
Required Skills:
SHELL SCRIPTINGPERLDIGITAL DESIGN
