Employer Active
Role : Design Verification Engineer
Location Sunnyvale , CA
JD for verification below:
Responsibilities:
As part of the verification team, you will work closely with Design and Architecture teams to review specifications and architecture, extract features and define verification plan including the coverage model
You will then execute on this plan through testbench development, directed/constrained random test generation, assertion-based verification, failure analysis and resolution, and coverage analysis and closure
You will run RTL and gate level functional simulations
You will also have the opportunity to support scripted automation flows to enhance the verification methodology
Qualifications:
MUST HAVE: Coding experience in System Verilog or Verilog
MUST HAVE: Advanced knowledge of HVL methodology (UVM)
Knowledge of standard ASIC design and verification flows including RTL design, simulation and testbench development
Solid understanding of reusable verification framework
Solid problem solving skillset
BSEE/BSCE + 3 years of relevant experience or MSEE/MSCE
Full Time