Digital Design Engineer

الرياض - السعودية

الراتب شهرياً: لم يكشف

تاريخ النشر: نُشرت منذ أكثر من 30 يومًا

عدد الوظائف الشاغرة: 1 عدد الوظائف الشاغرة

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ملخص الوظيفة

Movandi has made a big impact on 5G in a short amount of time from foundational research and innovative modular high efficiency mmWave system design to the introduction of our BeamXR 5G system that delivers improvements in performance coverage and latency to connect 5G everywhere. Now more than ever 5G--supported by Movandi technology--is becoming an integral part of the telecommunications landscape. And were only getting started.

At Movandi we work as a team. We like hard problems and solving them with the sharpest people. Are you looking to make a difference on the future of technology At Movandi you will help solve the growing challenges of deploying 5G millimeter wave networks. You will make an impact.

About the Role

Were looking for a graduate Digital Design Engineer to join our hardware team and help build highperformance digital systems. Youll design simulate and verify RTL modules in VHDL or Verilog contribute to FPGA/ASIC development and collaborate across hardware embedded software and verification to deliver reliable testable designs.

What Youll Do

RTL design: Implement synthesizable wellstructured RTL in VHDL or Verilog for FPGA or ASIC targets.
Simulation & verification: Write testbenches run simulations (e.g. ModelSim/Questa Xcelium VCS) debug waveforms and close functional coverage.
Documentation: Produce clear design specs interface docs and verification plans; contribute to design reviews.
Lab bringup: Assist with hardware validation and debug using oscilloscopes logic analyzers JTAG and boards.
Quality & processes: Use version control issue trackers and CI. Follow coding guidelines and contribute to continuous improvement.

MustHave Qualifications

Degree: Bachelors in Electrical/Electronic Engineering Computer Engineering or related field (recent graduate).
HDL proficiency: VHDL or Verilog Comfortable writing synthesizable RTL and basic testbenches.
Digital fundamentals: Strong grasp of synchronous design FSMs pipelining resets clock domains CDC and metastability.
Tools familiarity: At least one of: Vivado Quartus Radiant or Diamond for FPGA or exposure to Synopsys/Cadence/Mentor/Siemens toolchains in coursework.
Timing & constraints: Basic understanding of STA timing paths (setup/hold) and constraint files (SDC/XDC).
Scripting & workflow: Exposure to Python/Tcl/Make for automation. Comfortable in Linux development environments.
Communication & teamwork: Clear written/spoken communication collaborative mindset willingness to learn.

NicetoHave (Preferred)

Experience with UVM/OVM/SystemVerilog verification methodologies.
Knowledge of AXI/AHB SPI/I²C/UART PCIe/Ethernet/DDR interfaces.
Familiarity with DSP blocks clocking resources and power/performance/area tradeoffs.
Exposure to C/C for embedded integration or firmware bringup.
Handson with boardlevel debug schematics or lab instrumentation.

Tools & Technologies

HDLs: VHDL Verilog (SystemVerilog for verification is a plus).
FPGA: Xilinx Vivado Intel Quartus Lattice Radiant; IP integrators and constraint management.
ASIC: Synopsys Design Compiler Cadence Genus/Innovus Siemens Calibre (exposure).
Simulation/Verification: ModelSim/Questa Synopsys VCS Cadence Xcelium cocotb/UVM (optional).
Workflow: Git CI/CD Python/Tcl scripting Linux shell; issue tracking (Jira/GitHub).

Required Experience:

About the Role

What Youll Do

RTL design: Implement synthesizable wellstructured RTL in VHDL or Verilog for FPGA or ASIC targets.
Simulation & verification: Write testbenches run simulations (e.g. ModelSim/Questa Xcelium VCS) debug waveforms and close functional coverage.
Documentation: Produce clear design specs interface docs and verification plans; contribute to design reviews.
Lab bringup: Assist with hardware validation and debug using oscilloscopes logic analyzers JTAG and boards.
Quality & processes: Use version control issue trackers and CI. Follow coding guidelines and contribute to continuous improvement.

MustHave Qualifications

Degree: Bachelors in Electrical/Electronic Engineering Computer Engineering or related field (recent graduate).
HDL proficiency: VHDL or Verilog Comfortable writing synthesizable RTL and basic testbenches.
Digital fundamentals: Strong grasp of synchronous design FSMs pipelining resets clock domains CDC and metastability.
Tools familiarity: At least one of: Vivado Quartus Radiant or Diamond for FPGA or exposure to Synopsys/Cadence/Mentor/Siemens toolchains in coursework.
Timing & constraints: Basic understanding of STA timing paths (setup/hold) and constraint files (SDC/XDC).
Scripting & workflow: Exposure to Python/Tcl/Make for automation. Comfortable in Linux development environments.
Communication & teamwork: Clear written/spoken communication collaborative mindset willingness to learn.

NicetoHave (Preferred)

Experience with UVM/OVM/SystemVerilog verification methodologies.
Knowledge of AXI/AHB SPI/I²C/UART PCIe/Ethernet/DDR interfaces.
Familiarity with DSP blocks clocking resources and power/performance/area tradeoffs.
Exposure to C/C for embedded integration or firmware bringup.
Handson with boardlevel debug schematics or lab instrumentation.

Tools & Technologies

HDLs: VHDL Verilog (SystemVerilog for verification is a plus).
FPGA: Xilinx Vivado Intel Quartus Lattice Radiant; IP integrators and constraint management.
ASIC: Synopsys Design Compiler Cadence Genus/Innovus Siemens Calibre (exposure).
Simulation/Verification: ModelSim/Questa Synopsys VCS Cadence Xcelium cocotb/UVM (optional).
Workflow: Git CI/CD Python/Tcl scripting Linux shell; issue tracking (Jira/GitHub).

Required Experience:

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عن الشركة

Movandi Corporation

About Movandi: Movandi has made a big impact on 5G in a short amount of time — from foundational research and innovative modular, high efficiency mmWave system design to the introduction of our BeamXR 5G system that delivers improvements in performance, coverage, and latency to co ... اعرض المزيد

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