Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team

Utility Computing (UC)
AWS Utility Computing (UC) provides product innovations from foundational services such as Amazons Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2) to consistently released new product innovations that continue to set AWSs services and features apart in the industry. As a member of the UC organization youll support the development and management of Compute Database Storage Internet of Things (Iot) Platform and Productivity Apps services in AWS including support for customers who require specialized security solutions for customers who require specialized security solutions for their cloud services.

Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time agoeven yesterday. Our custom chips accelerators and software stacks enable us to take on technical challenges that have never been seen before and deliver results that help our customers change the world.

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Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team youll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; were handling massive scale and rapid integration of emergent technologies. Were looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures while ensuring high design quality and making the right trade-offs.


Key job responsibilities
- integrate multiple subsystems into top level SOC ensure correct clock/reset/functional/DFT signal routing
- As a key member of the ASIC design team you will implement and deliver high performance area and power efficient RTL to achieve design targets and specifications.
- Analyze design microarchitecture or architecture to make trade-offs based on features power performance or area requirements.
- Develop micro-architecture implement SystemVerilog RTL and deliver synthesis/timing clean design with constraints.
- Perform lint and clock domain crossing quality checks on the design.
- Work with with architects other designers verification teams pre- and post-silicon validation teams synthesis timing and back-end teams to accomplish your tasks.

You will thrive in this role if you:
- Are familiar with scripting in Python
- Are proficient with assertions
- Have good debug skills to analyze RTL test failures
- Have a Learn and Be Curious mindset

About the team
Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team youll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; were handling massive scale and rapid integration of emergent technologies. Were looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures while ensuring high design quality and making the right trade-offs.

Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures and were building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough but kind code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future.

- 7 years of ASIC implementation synthesis STA and physical design in deep sub-micron nodes (16nm or smaller) experience
- 7 years of digital design in communication systems experience
- 7 years of full-custom analog or RF layout experience
- 7 years of wireless communications systems and implementation experience
- 8 years of creating and maintaining automation frameworks for Post-Silicon Flow experience
- 7 years of verification in communication systems experience
- 5 years of UVM C System C and scripting experience
- 3 years of emulation experience
- Bachelors degree in Electrical Engineering or a related field
- Bachelors degree in Electrical Engineering/Communications Engineering or experience designing digital communication systems
- Bachelors degree in Electrical/Communications Engineering or 7 years of analog or RF layout design experience
- Masters degree in Electrical Engineering or experience working in electrical engineering field
- Bachelors degree in Computer Science Computer Engineering or Electrical Engineering
- Knowledge of UVM and Matlab
- Knowledge of implementing chips with multiple power islands and power gating
- Knowledge of multiple access systems including OFDMA TDMA and CDMA
- Knowledge of end-to-end network system architecture from wireless physical layer to application endpoints
- Knowledge of serial protocols including SPI I2C I3C and UART
- Knowledge of Python and Embedded C programming
- Experience in communication theory OFDM MIMO Digital/Wireless Communication Systems or RF engineering
- Experience with current and upcoming RF standards in cellular (4G/5G) WiMAX 802.11ad microwave backhaul DVB-S2 / DVB-C or related broadband wireless standards
- Experience leading or solely developing methodology and scripts for physical synthesis
- Experience taping out chips that have gone into high volume production
- Experience developing products for volume production
- Experience low power design techniques
- Experience delivering products to volume production
- Experience in modem L1/L2 algorithms development and architectures
- Experience in developing link and system level simulators using MATLAB Python or C
- Experience in test setup automation using MATLAB Python or Pearl
- Experience with Agile TDD BDD CI and Git
- Experience developing PHY/MAC layer HW/SW targeting SoCs FPGAs and general-purpose processors
- Experience leading technical initiatives and key deliverables
- Experience with version control systems and CI/CD pipeline implementation
- Experience in Bare Metal Environment development including linker scripts page tables and NVIC

- Masters degree or Ph.D. degree in Electrical Engineering or related field
- Experience in RTL coding and debug as well as performance power area analysis and trade-offs
- Experience with modern ASIC/FPGA design and verification tools
- Experience with SOC bring-up and post-silicon validation

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