Product Owner Senior Consultant-w2

Job description

We are looking for an enthusiastic candidate for the position of Semiconductor Design expert Engineer to support PLM( product life cycle management ) team to use their knowledge of designing highspeed analog circuits in mixedsignal ASICs test chip and foundation IP development on latest technology nodes to help building PLM solutions for semiconductor companies. We are looking for a candidate with CMOS design modeling and layout experience who has successfully tapped out several ASIC IPs and test chip designs.

Knowledge required in the areas like

• Develop detailed circuit specifications for mixedsignal circuits.
• Design circuit architectures and transistorlevel topologies to meet performance requirements.
• Provide guidance for physical implementation (layout) of highspeed circuits.
• Optimize circuits via simulation (using Cadence EDA tools) across various process and operating conditions.
• Create cell/libraries models to be used for high level integrated functional and timing verification.
• Integrate circuit elements into large analog/mixedsignal ASICs.
• Participate in the characterization and testing of ASICs.
• Help build test chip and validate.
• Have good understanding of PDK and various components within PDK.

Basic Qualifications & Skills

• Involved in all phases of multiple IC developments from specification to product introduction.
• Thorough knowledge of highfrequency broadband Analog MixedSignal IC design covering both electrical and physical aspects.
• Expertise in chip toplevel logic and physical design specializing in timingaware logical partitioning floor planning and fast timing closure for mixedsignal chips.
• Proficient in analog and mixedsignal modeling and verification for complex ICs emphasizing functional and timing models as well as physical abstraction generation.
• Solid understanding of Cadence RTL/STA/SDF gatelevel verification flows.
• Experience with standard and custom cell/IP cell library build characterization quality assurance and release processes.
• Collaborated extensively with EDA vendors to enhance tools and design flows including Hard IP integration methodology.
• Skilled in IC characterization at high frequency circuits using tools such as highspeed sampling oscilloscopes spectrum analyzers VNAs and signal sources.
• Desired experience in CMOS FinFET (16nm or lower) design.
• Verilog or VerilogA modeling proficiency is a plus.

Any exposure to PLM tools would be plus