Senior Chip Design Engineer , Graviton

Annapurna Labs is a fabless semiconductor company founded by industry veterans. We develop leading-edge products on state-of-the-art process technologies and were looking for talented engineers to help us build a semiconductor platform based on a revolutionary architecture.
Youll help develop state-of-the-art products within a disruptive system architecture working on the technologies that power the worlds largest cloud provider in a dynamic open and fast-paced environment. AWS provides a highly reliable scalable low-cost cloud infrastructure platform that powers hundreds of thousands of businesses in 190 countries.

AWS Graviton is a family of processors designed to deliver the best price performance for cloud workloads running in Amazon Elastic Compute Cloud (Amazon EC2). Graviton is designed in-house. It has reshaped what EC2 offers AWS customers and has become their preferred choice for cloud compute.
Youll join the Chip Design team on the Graviton product line. The team defines the products features and owns their architecture and development. We work closely with product definition pre- and post-silicon validation physical design software and other teams across the full chip development cycle from idea to mass production. Your design will ship in Graviton products deployed in AWS data centers worldwide so your work will have large-scale impact.
At Annapurna Labs youll play a key role in developing the next generation of semiconductor platforms for the worlds largest cloud infrastructure and in shaping the future of cloud computing.

Watch these videos to learn more about Annapurna Labs and the Graviton project:

* AWS re:Invent 2025 - Keynote with Peter DeSantis and Dave Brown:
* AWS re:Invent 2025 - AWS Graviton:



Key job responsibilities
Act as the technical lead for a major SoC domain across its full lifecycle from feature definition through tape-out and silicon bring-up
Work with Product Definition and Architecture to turn product requirements into feature specifications for your domain
Lead micro-architecture definition and own power performance and area trade-offs working with Physical Design and Software
Drive RTL design in Verilog/SystemVerilog and lead design reviews for the domain
Define and execute IP integration strategies
Set verification priorities with the Verification and Emulation teams and lead system-level and post-silicon debug for your domain
Carry design learnings into the next Graviton generations and improve design methodology and flows
Mentor and technically guide engineers working in your domain raising the technical bar of the team

About the team
Annapurna Labs started in 2011 as a fabless chip start-up focused on bringing innovation to the fast-growing cloud infrastructure. Four years after its inception Annapurna Labs was acquired by Amazon Web Services (AWS). Since then we have accelerated innovation and developed a number of products that benefit cloud customers including AWS Nitro technology AWS Graviton processors AWS ML Inferentia & Trainium and more. Although Annapurna Labs is a small company it is significant for AWS with a reputation of being the key ingredient in the secret sauce behind its success. The Annapurna Labs team is responsible for building custom chips accelerators and software stacks that run on top of them which gives us the possibility to optimize and improve our products in different layers more effectively.
We are a dynamic group of engineers dedicated to pushing the boundaries of semiconductor innovation. Our team combines the agility of a startup with the resources of Amazon Web Services creating a unique environment where breakthrough technologies are born. We collaborate across disciplines from product definition to silicon validation ensuring each chip represents the pinnacle of performance and reliability.

- 5 years of experience in Chip Design
- Track record of owning a design domain from specification through tape-out
- Proficient in Verilog/SystemVerilog
- . degree in Computer Engineering/Computer Science/Electrical Engineering
- Strong technical communication and mentoring capabilities
- Ability to lead technical work across teams and influence design decisions

- . in a technical-related field
- Experience across multiple tape-outs including post-silicon bring-up and debug
- Experience defining architecture and micro-architecture for complex SoC features
- Experience with IP integration and full chip development
- Protocols: PCIe DDR AXI CHI Ethernet
- Hands-on design experience with hardware support for virtualization and IO virtualization (e.g. hypervisors Arm virtualization extensions two-stage address translation IOMMU/SMMU)

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