Wireless Radio Verification Engineer

Join Apples Wireless Connectivity team developing state-of-the-art WiFi SoCs that power hundreds of millions of Apple products worldwide. Youll be part of our vertically integrated organization shaping next-gen wireless technology from concept through production. As a Wireless Radio Verification Engineer youll ensure first-time-right silicon success through sophisticated testbenches comprehensive scenarios and cutting-edge verification methodologiesenabling multi-gigabit wireless technology connecting the world!

As a Wireless Radio Verification Engineer youll verify Radio digital controllers combined with RF subsystems that enable exceptional wireless performance. Youll develop verification environments for complex radio control / transceiver paths spanning PLLs DAC / ADC data paths power management and co-existence mechanisms. This role emphasizes digital verification while bridging to RF/analog domainsyoull work closely with Design RF PHY and Systems teams to understand radio specifications and develop comprehensive test strategies. Youll own subsystem verification from test planning through coverage closure building testbench components and scenarios that exercise complex radio control sequences and operating modes.

Verify Radio digital controllers or subsystems from test planning environment bring-up through feature UVM testbench environments bus functional models and infrastructure for radio control and datapath constrained random scenarios exercising radio protocols control sequences and state machine on digital mixed-signal verification using SystemVerilog analog behavioral and/or DMS/real-number models to validate radio control closure by tracking regressions debugging issues and addressing coverage with cross-functional Design RF and Systems teams to define verification Python automation supporting verification flows and regression infrastructure.

Minimum requirement of a bachelors of ASIC verification flows with SystemVerilog including UVM testbench development scenario creation and RTL developing verification environments bringing up designs in simulation and debugging functional with digital design fundamentals Verilog or with scripting languages such as Python or problem-solving abilities and collaborative approach to engineering challenges.

Experience with digital controllers subsystems or data paths. nExperience with constrained random testing functional coverage implementation UVM methodology and assertion-based to mixed-signal modeling concepts including real-number to RF/analog system design such as LNAs Mixers PLLs amplifiers LDOs DAC / with Python Perl Bash or similar scripting for teammate with excellent communication skills and desire to seek diverse technical challenges.