TOP Design Verification Engineer Intern

About the Company:

At SK Hynix Memory Solution were at the forefront of semiconductor innovation developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies we drive the evolution of advancing mobile technology empowering cloud computing and pioneering future technologies. Our cutting-edge memory technologies are essential in todays most advanced electronic devices and IT infrastructure enabling enhanced performance and user experiences across the digital landscape.

Were looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory youll be part of a team thats pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. Were not just adapting to technological change were driving it with significant investments in artificial intelligence machine learning and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of whats possible in semiconductor technology we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

Internship Duration: 6 months

Hours: 40 hours per week

Start Date: Immediately (September 2026 /October 2026)

Location: San Jose

Responsibility :

• Study the Microarchitecture of the Design (SOC TOP) and list the Verification Requirements
• for testing.
• Modify the Test Bench for the SOC TOP level testing.
• Create/Modify Tests Cases to test the functionalities of the SOC.
• Debug & identify the issue & file bug reports to Designer.
• Testing to meet the Coverages (Functional Toggle) criteria.

Minimum requirements :

• A Bachelors or Masters degree in Electrical Engineering (BSEE/MSEE) or a related field is required.
  
• Digital IC Design & Verification experiences.
• Work in Windows and Linux environment.
• Python or Perl scripting experience.
• Experience in System Verilog UVM C/Assembly coding
• Experience in Perforce and Confluence.
• Familiarity with UCIe CPU architecture NAND protocols and AI productivity tools is a plus.

COMPENSATION: $35/hr - $45/hr