Test Engineering Director

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

• Define and lead the overall test engineering strategy for IO Chiplet-based products targeting high-speed and high-power AI applications including ATE platform selection vendor engagement and outsourced manufacturing test strategy.
• Drive strategic partnerships with Tier 1 ATE vendors OSATs probe card suppliers and instrumentation providers to develop next-generation test solutions enabling scalable mass production of advanced semiconductor products.
• Lead cross-functional and multi-disciplinary engineering teams across silicon design package engineering product engineering systems manufacturing and reliability organizations to develop robust test infrastructure and production manufacturing flows.
• Build and manage high-performing engineering teams responsible for customer sample validation silicon characterization correlation qualification yield improvement and high-volume manufacturing test deployment.
• Architect scalable and reusable ATE IP software frameworks and automation methodologies that can be efficiently adapted across multiple product families and packaging architectures including MCM CPC and CPO platforms.
• Lead ATE hardware architecture load board design probe card strategy socket validation and system verification to ensure excellent repeatability reproducibility signal integrity power integrity and thermal performance for high-speed/high-power devices.
• Drive continuous improvement initiatives focused on test cost reduction throughput optimization test time reduction DFT/DFM enhancement manufacturing efficiency yield improvement and production quality control.
• Define and implement data-driven methodologies for yield analytics failure analysis correlation and production monitoring across wafer sort final test and system-level test operations.
• Ensure complete and accurate documentation of test hardware software validation methodologies and manufacturing procedures within centralized document and configuration management systems.

What Were Looking For

• Bachelors Masters or Ph.D. degree in Electrical Engineering Computer Engineering Optical Engineering Computer Science or related disciplines. Formal certification or advanced training in ATE software architecture automation frameworks or semiconductor test methodologies is highly desired.
• Extensive technical leadership experience in high-speed and high-power semiconductor test development for AI networking or advanced compute applications.
• 12 years of experience in semiconductor test engineering including 6 years leading engineering teams responsible for new product introduction (NPI) ATE development characterization correlation and high-volume manufacturing.
• Proven track record leading cross-functional organizations across silicon design package design product engineering systems reliability and manufacturing teams to develop scalable ATE solutions and production test strategies.
• Strong experience defining ATE architecture and reusable ATE IP platforms that can be efficiently adapted across multiple product families including chiplet-based MCM CPC and CPO products.
• Demonstrated leadership in CAPEX/OPEX planning resource forecasting organizational scaling recruiting and long-term technology roadmap definition for executive management.
• Experience driving end-to-end wafer sort package test and system-level test strategies for advanced heterogeneous integration products.

Preferred Qualifications

• Deep experience with high-speed IO and die-to-die interface characterization including PCIe Serdes UCIe HBM CXL and proprietary interconnect technologies.
• Hands-on experience developing ATE solutions for advanced packaging technologies including:
  • Multi-Chip Module (MCM)
  • Co-Packaged Copper (CPC)
  • Co-Packaged Optics (CPO)
  • 2.5D/3D heterogeneous integration
• Strong background in wafer probe hardware high-speed load board design socket design signal integrity power integrity and thermal optimization for high-current AI devices.
• Experience with high-speed digital test methodologies including frequency-domain and time-domain measurements up to 100GHz and beyond.
• Knowledge of chip-to-chip communication protocols and embedded device management interfaces such as I2C SPI JTAG MDIO eFuse ADC/DAC calibration and telemetry systems.
• Hands-on expertise with automated test platforms including Advantest 93K and Teradyne UltraFLEX.
• Strong software development skills with production deployment experience in Python C/C and Java.
• Experience architecting scalable test executive frameworks reusable software libraries and revision-controlled ATE infrastructure for global manufacturing deployment.
• Proven track record building mentoring and leading high-performing engineering organizations focused on innovation execution and operational excellence.

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.