Test Architect (CTD San Jose, CA)

We are the global test and automation specialists powering next-generation technologies through sophisticated solutions. Behind every electronic device you use Teradynes test technology ensures your device works right the first time every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly efficiently and cost-effectively. TogetherTeradynecompanies deliver manufacturing automation across industries and applications around the world!

We attract develop and retain a high-performance workforce comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees and communities thrive.

Our Purpose
TERADYNE where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supportedto innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths views and experiences. We believe that our differences enable us to be a better team one that makes better decisions drives innovation and delivers better business results.

Opportunity Overview

Teradyne is seeking a Test Architect to lead test engineering activities for strategic semiconductor test customers. You will partner with customers product engineers test engineers application engineers and platform teams to translate device requirements into practical production-ready test solutions.

This hands-on role combines customer engagement deep test expertise and technical leadership. You will define test strategies guide implementation and validation resolve difficult product and production problems and build reusable approaches that improve quality test time coverage and engineering efficiency across programs.

• Serve as the test architecture for assigned strategic customers. Clarify product test requirements device risks quality goals manufacturing constraints schedule drivers and technical tradeoffs.

• Define end-to-end test strategies covering test content coverage insertions instrumentation interface requirements multisite execution datalogging correlation characterization and production release.

• Turn architectural direction into executable plans with clear test partitions interfaces implementation stages validation gates risk retirement activities and measurable acceptance criteria.

• Guide implementation through feasibility studies prototypes test plan and test program reviews silicon debug characterization correlation and resolution of complex yield quality or production issues.

• Design for accurate and repeatable measurement. Establish approaches for calibration uncertainty limits guardbands repeatability reproducibility and correlation.

• Optimize the complete test solution across coverage quality test time throughput parallel efficiency hardware utilization maintainability and cost without compromising product requirements.

• Develop reusable test methods patterns flows design guidelines validation assets and debug practices. Convert recurring customer needs into scalable capabilities instead of one off account solutions.

• Coach test and software engineers in architecture and disciplined test development. Provide reviews examples and practical guidance that strengthen independent technical judgment and execution.

• Represent Teradyne in customer workshops architecture reviews escalations and account planning. Explain risks and tradeoffs clearly and build alignment across technical and business stakeholders.

Core expertise

• Test strategy: Device requirements structural and functional coverage insertion strategy fault isolation characterization correlation guard banding and production readiness.

• Test implementation: Semiconductor test program architecture instrument selection and control digital patterns DC and mixed-signal methods multisite execution datalogging and debug.

• Product and manufacturing integration: DFT interfaces DIBs handlers probers factory systems data analytics high volume manufacturing and cross-site deployment.

• Architecture: Measurement integrity quality coverage reliability test time throughput reuse maintainability extensibility and long term supportability.

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If youre ready to join us in this mission take a closer look at the minimum criteria for the position.

• Bachelor degree in Electrical Engineering Computer Engineering Applied Physics or equivalent practical experience.

• At least 7 years of semiconductor test engineering experience including experience defining test strategy or leading technical direction for complex products or programs.

• Strong knowledge of automated test equipment semiconductor devices test methods instrument capabilities test program structure and production test constraints.

• Practical experience with test development silicon bring-up characterization correlation multisite validation production release and test time optimization.

• Ability to translate product requirements and failure risks into test coverage evaluate alternatives document decisions and explain tradeoffs to different audiences.

• Experience leading through technical influence collaboration and mentorship across customer product hardware software and manufacturing teams.

• Confidence working directly with customers during architecture discussions escalations and schedule sensitive silicon or production issues.

• Strong analytical written presentation and facilitation skills.

• Located in or willing to relocate to San Jose CA with ability to travel up to 25% and collaborate globally.

Preferred qualifications

• Master degree in Electrical Engineering Computer Engineering Applied Physics or a related discipline.

• Deep experience with digital power protocol-aware memory RF or mixed-signal semiconductor test.

• Experience with DFT scan BIST pattern generation device characterization statistical limit setting yield analysis or adaptive test.

• Experience architecting test solutions for advanced packaging chiplets high site count high power high speed interfaces or constrained production environments.

Compensation:
The base salary range for this role is$170500 to range is a good faith estimate and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Benefits:

Teradyne offers a variety of robust health and well-being benefit programs including medical dental vision Flexible Spending Accounts retirement savings plans life and disability insurance paid vacation & holidays tuition assistance programs and more. Please click here to see details.

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