System High-Speed IO Validation Engineer

This is a system-level validation role within the Mac and Data Center Hardware organization focused on SerDes I/O validation across multiple platforms. You will be responsible for setting up and executing high-speed I/O validation driving electrical compliance bring-ups and stress testing I/Os in system environments while collecting and analyzing key metrics. The role also includes high-speed validation and electrical compliance testing of I/Os for form-factor systems as well as validation of high speed cables and will work closely with cross-functional teams including system signal integrity silicon design and system design to ensure robust and reliable I/O performance. If you have hands-on high-speed lab experience and are eager to grow your expertise in system level signal integrity validation we want to hear from you.

In this role you will:nExecute high-speed serial I/O validation across multiple high-speed electrical compliance testing and organize compliance data reports for comparison against specifications and approval by certified and triage issues with compliance test hardware fixtures software and the Device Under Test (DUT).nPerform failure analysis and provide feedback to support iterative hardware design and software tunable and develop stress testing methodologies to identify design operating limits of serial I/Os post system high-speed fixtures connectors cables and platforms I/ Python-based scripts to automate data collection and accelerate validation workflows.

M.S. or B.S. Degree with at least 2 years of lab work with different aspects of Signal Integrity for high-speed SerDes parallel bus and single-ended of high-speed channel characteristics including insertion loss return loss crosstalk and impedance -on experience with high-speed SerDes validation such as for PCIe DP or USB4/-on experience and familiarity with lab high-speed equipment including oscilloscopes BERTs TDR and VNA/PNA including calibration methods.

M.S. Degree with 5 years of relevant work to understand and review channel analysis from Signal Integrity EDA toolsnDeep knowledge of system-level SerDes design and analysis skills including understanding of transmitter and receiver equalization methods (such as FFE CTLE DFE VGA gain) CDR behaviors link training algorithms and eye margining tools.