Staff SoC DFT Engineer, HBM

Job Description

• Own SoClevel design for test (DFT) architecture and implementation including scan memory builtin selftest (MBIST) logic builtin selftest (LBIST) where applicable boundary scan (Joint Test Action Group JTAG) and test access architectures for HBM basedie designs.
• Define and drive DFT architecture early in the design cycle ensuring alignment with SoC integration floorplanning timing power and physical design requirements.
• Implement and integrate DFT logic at block subsystem and fullchip levels while partnering closely with registertransfer level (RTL) design and SoC integration teams.
• Execute and sign off DFT flows including linting clockdomain crossing (CDC) checks DFT rule checks automatic test pattern generation (ATPG) readiness and coverage closure.
• Collaborate with physical design teams to optimize DFT solutions for placement routing timing closure and design rule check/layout versus schematic (DRC/LVS) signoff.
• Work with verification product engineering test probe and manufacturing teams to ensure testability diagnosability smooth presilicon debug and postsilicon bringup.
• Partner with computeraided design (CAD) and methodology teams to standardize and improve DFT flows contribute to crossgroup technical reviews mentor engineers as appropriate and drive innovation for future HBM generations.

• Strong handson experience with SoC design for test (DFT) architecture and implementation including scan insertion MBIST/LBIST concepts boundary scan (JTAG) and ATPG.
• Experience working across full RTLtoGDS SoC flows and collaborating with synthesis static timing analysis (STA) and physical design teams.
• Proficiency using industrystandard electronic design automation (EDA) tools from Siemens Synopsys and/or Cadence for DFT and implementation.
• Bachelors degree in Electrical Engineering Computer Engineering or a related field or equivalent practical experience.
• Seven or more years of relevant experience in SoC design DFT or implementation for complex digital applicationspecific integrated circuits (ASICs) or SoCs.

• Experience with large complex SoCs that integrate multiple intellectual property (IP) blocks and subsystems.
• Strong RTL debugging design analysis and problemsolving skills.
• Experience using scripting languages such as Python Tcl or Perl for flow automation.
• Ability to communicate clearly and collaborate effectively across global crossfunctional teams.
• Familiarity with memory systems such as dynamic randomaccess memory (DRAM) highbandwidth memory (HBM) and related JEDEC specifications.