Staff Engineer, RTL Design

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Staff Engineer RTL Design

Overview

The Memory Solutions Lab (MSL) is part of Samsungs Memory Business Unit the industrys technology and volume leader in DRAM NAND Flash SRAM memory. MSLs vision is to solve key problems and optimize architecture solutions for Cloud & Data center environments. We are an integral part of Samsungs strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

Youll Do

The Candidate will be a key technical member of MSL Datacenter Device Solutions (DCDS) Group. He or she will join a team of experts in researching and developing innovative data center/ cloud networking storage and compute technologies and system solutions. The ideal candidate preferred to have prior experience developing leading edge solutions for at least one of the areas: memory hierarchy storage networking or embedded computing.

Location: Daily onsite presence at our San Jose CA office in alignment with our Flexible Work polic

Job ID: 42940

• Microarchitecture RTL design and verification.
• Develop new RTL IP for high performance PoCs.
• Lab bring-up lab test and validation of RTL IPs.
• Research next generation memory and storage controller features.
• Research emerging technology standards.
• Work with hardware/ software architects developing one-of-a-kind innovative FPGA prototypes and contribute to feasibility studies & developing solutions.
• Assist software architects developing Linux/ Windows device driver test and debug.
• Participate in value proposition studies publish papers in leading journals and conferences and file patents.
• Complete other responsibilities as assigned.

What You Bring

• B S. with 10 years of experience in RTL development or M.S with 8 years of experience or Ph.D. with 5 years in Computer Engineering or Electrical Engineering preferred.
• Familiarity with FPGA design tool flows synthesis timing analysis partitioning FPGA programming bring up and testing is a plus.
• In-depth background in HDL development Verilog coding integration synthesis debug simulation test bench creation and debug using CAD tools (Synopsys Mentor Cadence tools).
• Hands-on experience with hardware board bring-up server system integration and software integration.
• Experience and exposure to PCIe CXL NVMe AXI DDR4/5 Ethernet protocols.
• Must be highly motivated with excellent verbal and written communication skills.
• Demonstrated attention to detail.
• Ability to meet aggressive project deadlines in a team environment.
• Ability to work successfully with cross-functional teams including coordinating across organizational boundaries and geographies.
• Youre inclusive adapting your style to the situation and diverse global norms of our people.
• An avid learner you approach challenges with curiosity and resilience seeking data to help build understanding.
• Youre collaborative building relationships humbly offering support and openly welcoming approaches.
• Innovative and creative you proactively explore new ideas and adapt quickly to change.

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