Sr IC Digital Layout Designer
Job Location:
Job Location:
Redmond, WA - USA
Monthly Salary:
$ 130000 - 160000
Monthly Salary:
Posted on:
2 days ago
Posted on:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Job Title: Senior Digital Layout Designer
Location: Hybrid / On-site (Flexible based on project needs)
Employment Type: Full-time
Overview
We are seeking an experienced Senior Digital Layout Designer to join a cutting-edge engineering team focused on delivering high-performance silicon-based this role you will be responsible for the physical layout design of complex digital and mixed-signal integrated circuits ensuring optimal performance manufacturability and compliance with advanced process technology nodes.
You will collaborate closely with circuit designers verification engineers and process integration teams to translate schematic designs into high-quality production-ready layout implementations.
Key Responsibilities
Develop and execute full-chip and block-level physical layout for advanced digital and mixed-signal IC designs.
Work with circuit designers to interpret schematics and ensure accurate layout implementation.
Perform floorplanning placement routing and optimization for performance area and power efficiency.
Ensure strict adherence to design rules (DRC) layout vs schematic (LVS) and electrical rule checks (ERC).
Collaborate with verification teams to debug and resolve layout-related issues.
Optimize layouts for signal integrity timing closure and manufacturability.
Support tape-out activities and coordinate with foundries on layout-related requirements.
Contribute to layout methodology improvements and automation initiatives.
Mentor junior layout designers and provide technical guidance as needed.
Required Qualifications
Bachelors or Masters degree in Electrical Engineering Electronics Engineering or related field.
7 years of experience in digital IC layout design in advanced technology nodes.
Strong expertise in industry-standard EDA tools (e.g. Cadence Virtuoso Synopsys tools or equivalent).
Deep understanding of CMOS process technology and physical design principles.
Proven experience with DRC/LVS closure and debugging complex layout issues.
Strong knowledge of parasitic effects timing considerations and signal integrity.
Experience working in multi-disciplinary semiconductor design teams.
Preferred Qualifications
Experience with FinFET or sub-10nm technology nodes.
Exposure to low-power design techniques and high-speed digital circuits.
Familiarity with layout automation scripting (Skill Python TCL or similar).
Experience supporting multiple tape-outs in production environments.
The anticipated annual base salary for this position is between $130000 to $160000 which also includes a comprehensive benefits package.
Full-Time Benefits:
15 days of PTO per calendar year
10 paid Holidays per calendar year
Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
Dental & Vision: Company covers 50% of premiums for Employee and Dependents
Voluntary Benefits: Life Insurance FSA (Health and Dependent Limited Purpose) HAS and Gap Insurance
Employee Assistant Program (EAP)
401k - Traditional & Roth
Life/AD&D and Long-Term Disability
Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race religion creed color age sex sexual orientation gender gender identity or expression national origin genetics ancestry marital status civil union status medical condition disability (mental and physical) military and veteran status pregnancy childbirth and related medical conditions or any other characteristic protected by applicable federal state or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Location: Hybrid / On-site (Flexible based on project needs)
Employment Type: Full-time
Overview
We are seeking an experienced Senior Digital Layout Designer to join a cutting-edge engineering team focused on delivering high-performance silicon-based this role you will be responsible for the physical layout design of complex digital and mixed-signal integrated circuits ensuring optimal performance manufacturability and compliance with advanced process technology nodes.
You will collaborate closely with circuit designers verification engineers and process integration teams to translate schematic designs into high-quality production-ready layout implementations.
Key Responsibilities
Develop and execute full-chip and block-level physical layout for advanced digital and mixed-signal IC designs.
Work with circuit designers to interpret schematics and ensure accurate layout implementation.
Perform floorplanning placement routing and optimization for performance area and power efficiency.
Ensure strict adherence to design rules (DRC) layout vs schematic (LVS) and electrical rule checks (ERC).
Collaborate with verification teams to debug and resolve layout-related issues.
Optimize layouts for signal integrity timing closure and manufacturability.
Support tape-out activities and coordinate with foundries on layout-related requirements.
Contribute to layout methodology improvements and automation initiatives.
Mentor junior layout designers and provide technical guidance as needed.
Required Qualifications
Bachelors or Masters degree in Electrical Engineering Electronics Engineering or related field.
7 years of experience in digital IC layout design in advanced technology nodes.
Strong expertise in industry-standard EDA tools (e.g. Cadence Virtuoso Synopsys tools or equivalent).
Deep understanding of CMOS process technology and physical design principles.
Proven experience with DRC/LVS closure and debugging complex layout issues.
Strong knowledge of parasitic effects timing considerations and signal integrity.
Experience working in multi-disciplinary semiconductor design teams.
Preferred Qualifications
Experience with FinFET or sub-10nm technology nodes.
Exposure to low-power design techniques and high-speed digital circuits.
Familiarity with layout automation scripting (Skill Python TCL or similar).
Experience supporting multiple tape-outs in production environments.
The anticipated annual base salary for this position is between $130000 to $160000 which also includes a comprehensive benefits package.
Full-Time Benefits:
15 days of PTO per calendar year
10 paid Holidays per calendar year
Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
Dental & Vision: Company covers 50% of premiums for Employee and Dependents
Voluntary Benefits: Life Insurance FSA (Health and Dependent Limited Purpose) HAS and Gap Insurance
Employee Assistant Program (EAP)
401k - Traditional & Roth
Life/AD&D and Long-Term Disability
Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race religion creed color age sex sexual orientation gender gender identity or expression national origin genetics ancestry marital status civil union status medical condition disability (mental and physical) military and veteran status pregnancy childbirth and related medical conditions or any other characteristic protected by applicable federal state or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Required Experience:
Senior IC
About Company
Encore Semi provides engineering services and solutions to the Semiconductor and Electronics industries, using highly advanced technologies and tools. Our Teams of Engineers provide custom engineering solutions for semiconductor product companies, OEMs developing IP or SoC, and Subsy ... View more
