SoC Physical Design Engineer, PnR
Job Location:
Job Location:
San Jose, CA - USA
Monthly Salary:
Not Disclosed
Monthly Salary:
Posted on:
27 days ago
Posted on:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Imagine what you could do here! At Apple new ideas have a way of becoming extraordinary products services and customer experiences very quickly. Bring passion and dedication to your job and theres no telling what you could accomplish. Dynamic hardworking people and inspiring innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product!nnIn this visible role you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology.
Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.n Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.n Timing physical and electrical verification and driving the signoff closure for the partitions.n Resolve and improve design and flow issues related to physical design identify potential solutions and drive execution.
Minimum BS and 3 years of relevant industry with partition level Pu0026R implementation including floorplanning clock and power distribution timing closure physical and electrical of physical design construction and analysis flows and with industry standard tools understanding their capabilities and underlying algorithms.
Ability to adhere to stringent schedule and die size with large SOC designs (u003e20M gates) with frequencies in excess of with sub 10nm tech communication skills.
Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.n Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.n Timing physical and electrical verification and driving the signoff closure for the partitions.n Resolve and improve design and flow issues related to physical design identify potential solutions and drive execution.
Minimum BS and 3 years of relevant industry with partition level Pu0026R implementation including floorplanning clock and power distribution timing closure physical and electrical of physical design construction and analysis flows and with industry standard tools understanding their capabilities and underlying algorithms.
Ability to adhere to stringent schedule and die size with large SOC designs (u003e20M gates) with frequencies in excess of with sub 10nm tech communication skills.
Required Experience:
IC
About Company
Ask Siri to name the most successful company in the world and it might respond: Apple. And it's not just out of familial pride. Apple consistently ranks highly in profit, revenue, market capitalization, and consumer cachet. In 2018, the company became the first reach a trillion dollar ... View more
