Silicon ValidationEmulation Design Engineer

As a Silicon Validation/Emulation Design Engineer you will work in a team developing Wireless SoCs with custom hardware accelerators as well as multiple ARM-based sub-systems. You will be a key contributor in our pre-silicon hardware validation efforts using Cadence Palladium emulation platforms enabling early system integration and hardware validation. You will work closely with SoC architects RTL designers and verification engineers to ensure our designs are thoroughly validated before tape-out. You will help define the processes methods and tools for emulation environment development and debug of large complex you enjoy a fast-paced and ambitious environment collaborating with people across different functional areas and thriving during crisis times we encourage you to apply and join us!

In this role youll be responsible for the following: n- Building and maintaining Palladium emulation environments including compile flows netlist preparation memory modeling and clock/reset configurations.n- System-level debug and root cause analysis of complex hardware issues on the emulation platform.n- IP-level debug and validation working closely with IP owners to isolate and resolve design issues.n- Development and implementation of automation aids flows and scripts to improve Palladium build efficiency debug turnaround and platform utilization.n- Performance profiling and optimization of emulation models to maximize execution speed.n- Collaboration with multi-disciplinary groups to make sure emulation deliverables are on schedule and support critical program milestones.

Own and maintain Palladium emulation build flows for SoC and subsystem-level debug and triage of emulation model issues working with RTL designers and verification system-level hardware validation efforts and hardware reusable debug methodologies and collateral to accelerate issue emulation model performance through compile tuning partitioning strategies and platform document flows debug procedures and best with cross-functional teams to define emulation requirements and support prototype hardware validation.

BS and a minimum of 10 years relevant industry experience

Proven experience with Cadence Palladium (or equivalent emulation platforms such as Synopsys ZeBu) including build flows compile optimization and platform bring-upnStrong debugging skills with experience in system-level and IP-level debug on emulation platformsnExperience with emulation compile flows including synthesis for emulation memory compilation clock modeling and I/O abstractionnProficiency in debug tools and methodologies (waveform analysis signal probing assertion-based debug transactors)nSolid understanding of RTL design concepts SoC architectures ARM-based subsystems and standard bus protocols (AXI AHB APB)nExperience developing and maintaining automation scripts (Python Tcl Perl Shell) to streamline emulation workflowsnStrong analytical and problem-solving skills with ability to debug complex system-level issuesnExperience with Wireless SoC applications (Wi-Fi Bluetooth cellular) - strongly preferrednExcellent communication and collaboration skills to work effectively across functional teamsnExperience with version control systems (Git Perforce) and CI/CD integration for emulation flows