Senior Staff Design Engineer Memory Subsystem COE

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

• Own and drive DDR/LPDDR/HBM subsystem micro-architecture definition RTL implementation and integration

• Collaborate closely with Architecture teams to translate requirements into robust RTL designs

• Work with Design Verification teams on test-plan reviews debug and coverage closure

• Partner with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTL

• Support silicon bring-up and post-silicon debug working with firmware and validation teams

• Drive design quality improvements coding best practices and reuse across projects

• Participate in design reviews milestone reviews and cross-functional technical discussions

• Mentor junior designers and provide technical leadership within the DDR/LPDDR/HBM design domain

What Were Looking For

• Bachelors degree in Electronics/Electrical Engineering with 5-10 years of relevant experience in RTL design or Masters and/or PhD with 3-5 yrs of relevant experience

• Proven experience delivering complex DDR LPDDR HBM controllers or subsystems from architecture through RTL closure

• Strong hands-on experience in System Verilog / Verilog RTL development

• Expertise/Familiarity in DDR/HBM JEDEC specifications

• Deep knowledge of ARM-based SoC integration and AMBA protocols (AXI-4 CHI ACE)

• Solid grasp of Clocking Resets CDC/RDC low-power techniques and performance optimization

• Experience supporting lint CDC/RDC synthesis and design sign-off flows

• Experience using industry-standard EDA tools from Synopsys Cadence Mentor/Siemens

• Proficient in scripting languages such as TCL / Perl / Python

• Experience with version control systems such as GIT SVN etc.

Additional Qualifications:

• Experience on end-to-end DDR/HBM subsystem RTL design execution and sign-off

• Experience designing high-performance low-latency data paths and handling ordering coherency and error mechanisms

• Proficient in debugging functional and performance issues at subsystem and SoC levels

• Familiarity with post-silicon bring-up and debug methodologies in collaboration with firmware and validation teams

• Prior experience mentoring engineers and providing technical leadership in a cross-functional environment

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.