Senior Principal Engineer – Hardware Chip Lead, Connectivity BU

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

Marvells Optical DSP (ODSP) team within the Connectivity Business Unit develops advanced industry-leading ASICs for the hyperscale data center enterprise and AI infrastructure markets. Our products including multi-terabit retimers coherent DSP devices and high-speed optical transceivers are critical enablers for efficient high-bandwidth data transmission across fiber optical networks and electrical interconnects at 100G per lane.
The ODSP team operates at the leading edge of semiconductor technology developing chips in TSMC advanced process nodes. We are a global multi-site engineering organization spanning Santa Clara Ottawa Pavia Irvine Vietnam and Argentina and we are looking for a senior experienced technical leader to serve as Hardware Chip Lead on our next-generation ODSP programs.

What You Can Expect

Chip Ownership & Program Leadership

Serve as the primary hardware technical owner for an ODSP chip program responsible for tracking and driving progress across all hardware design phases from POR (Plan of Record) through MPR (Mass Production)

Finalize the Product Requirements Document (PRD) and bring-up requirements in collaboration with architecture marketing and applications engineering teams

Represent hardware engineering at all key program milestones: Pre-PA PA PSM POR Design Reviews Tape-Out and MPR

Coordinate and align cross-functional teams including analog design digital design DV DFT physical design STA firmware validation ATE/test engineering product engineering and quality

Manage and communicate program status risks and mitigation plans to BU engineering leadership on a regular cadence

Technical Leadership

Provide technical leadership for the full chip design independently proposing and defining high-level technical solutions across the hardware stack

Set technical direction and drive resolution of complex cross-disciplinary design challenges spanning analog/digital integration high-speed SerDes DSP datapath and SoC architecture

Proactively identify technical risks early in the design cycle and drive mitigation strategies across functional teams

Take an active role in setting and prioritizing BU milestones and objectives; participate in architecture and design reviews at the chip and block level

Drive continuous improvement in design methodology flows and quality across the ODSP hardware organization

Design & Execution

Lead end-to-end chip design execution across advanced CMOS nodes (TSMC 2nm/3nm/5nm) including architecture RTL physical design DFT timing closure and tape-out

Own the chip bring-up plan and execution coordinating multi-site teams across global locations; drive Phase 0 Phase 1 and Phase 2 bring-up activities through to silicon validation

Oversee silicon validation PVT characterization ATE test program development qualification (ESD LU HTOL) and production release

Drive resolution of post-silicon issues coordinating debug across analog digital firmware and validation teams

Ensure all hardware deliverables including PRD design documentation and bring-up requirements are complete and on schedule

Mentorship & Knowledge Sharing

Mentor and develop engineers across the ODSP hardware organization; invest in building technical depth and breadth within the team

Foster a culture of knowledge sharing technical rigor and continuous learning

Coach and develop engineering talent; provide guidance and feedback to support career growth at all levels

What Were Looking For

Education & Experience

Bachelors degree in Electrical Engineering Computer Engineering or related field and 15 years of related professional experience

OR Masters degree in Electrical Engineering Computer Engineering or related field with 1012 years of experience

OR PhD in Electrical Engineering Computer Engineering or related field with 810 years of experience

Required Skills & Experience

Proven track record as a chip lead or equivalent technical owner on complex SoC/ASIC programs from architecture through tape-out and post-silicon productization

Deep expertise in high-speed mixed-signal SoC design including SerDes (100G/lane) DSP datapath analog/digital integration and advanced CMOS process nodes (5nm 3nm)

Strong understanding of the full ASIC design flow: micro-architecture RTL synthesis DFT physical design STA timing closure and tape-out

Experience leading and coordinating cross-functional hardware teams across analog digital DV DFT PD firmware validation and test engineering disciplines

Demonstrated ability to drive silicon bring-up debug and validation across multi-site global teams

Experience with ATE test program development silicon characterization qualification (HTOL ESD LU) and production release

Excellent communication interpersonal and presentation skills; ability to represent hardware engineering to BU leadership and cross-functional stakeholders

Highly motivated self-driven and able to manage ambiguity in a fast-paced multi-program environment

Preferred Skills

Familiarity with optical DSP coherent or direct-detect transceiver architectures or high-speed retimer products

Experience with eAVS (Adaptive Voltage Scaling) or similar power optimization subsystems

Knowledge of SiPho (Silicon Photonics) integration and module-level validation

Experience working in a multi-site globally distributed engineering organization

Expected Base Pay Range (USD)

182360 - 273200 $ per annum

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional comprehensive benefits that support our employees at every stage - from internship to retirement and through lifes most important moments. Our offerings are built around four key pillars: financial well-being family support mental and physical health and recognition. Highlights include an employee stock purchase plan with a 2-year look back family support programs to help balance work and home life robust mental health resources to prioritize emotional well-being and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.

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