Senior Physical Design Engineer

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Who We Are Physical Design Team in APD

Broadcoms ASIC Products Division (APD) is the global leader in custom high-performance silicon solutions. We partner with the worlds most innovative technology companiesspanning hyper-scale cloud providers AI pioneers and tier-1 networking infrastructure leadersto co-design and manufacture complex custom ASICs that power the modern digital backbone.

The Physical Design team within APD is the world-class execution engine behind the industrys most advanced custom silicon. We push the limits of silicon technology by combining deep architectural expertise advanced IP cutting edge physical design methodologies in 3nm/2nm nodes and advanced 2.5D/3D chiplet integration to solve the most demanding compute and bandwidth transform ultra-complex architectures into fully realized high-yielding first-pass silicon success.

Broadcom is searching for an Senior Physical Design Engineer to join the ASIC Products Division. This position involves working with the latest technology to continue driving next generation Artificial Intelligence and PCIe Switch Products. More specifically this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out.

Key Responsibilities

Full-Flow Implementation: Lead block-level and top-level implementation from floorplanning to GDSII stream-out using Cadence Innovus

Advanced Node Execution: Drive floorplanning placement CTS routing and timing/power optimization on advanced technology nodes (5nm 3nm 2nm) using multi-patterning and complex metal stacks.

Timing & Power Closure: Perform multi-corner multi-mode (MCMM) static timing analysis (STA) signal integrity (SI) optimization and power grid optimization (static/dynamic IR-drop EM) for signoff using PrimeTime Voltus or RedHawk.

Qualifications & Requirements

Education: B.S. or M.S. degree in Electrical Engineering Computer Engineering or a related technical field.

Experience: 8 years of hands-on physical design experience successfully taping out complex high-frequency ultra-large-scale networking or AI ASICs.

Deep Sub-Micron Expertise: Direct experience executing tapeouts in TSMC advanced nodes (N7 N5 N3) or equivalent foundry processes.

EDA Tool Mastery: High proficiency in major physical design tool flows:

P&R: Cadence Innovus

Timing/STA: Synopsys PrimeTime or Cadence Tempus

Extraction & IR/EM: StarRC / QRC RedHawk

DRC/LVS: Siemens Calibre

Automation Skills: Advanced TCL Python and Unix shell scripting for flow automation and database manipulation.

Communication: Excellent technical leadership problem-solving and cross-functional communication skills.

Preferred Qualifications

Strong background in high-speed clock network implementation (H-tree mesh low-power CTS).

Experience with power-aware implementation flows (UPF/CPF multi-voltage domains clock/power gating).

Compensation and Benefits

As a valued member of our team youll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant but also annual equity awards connecting your success directly to the companys growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical dental and vision plans 401(K) participation including company matching Employee Stock Purchase Program (ESPP) Employee Assistance Program (EAP) company paid holidays paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race color creed religion sex sexual orientation national origin citizenship disability status medical condition pregnancy protected veteran status or any other characteristic protected by federal state or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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