Senior PCB Design Layout Engineer

At Penguin Solutions (Nasdaq: PENG) The AI Factory Platform Company were building a team of innovators who thrive on collaboration creativity and the opportunity to help shape the future of AI. As part of the AI technology revolution our teams design build deploy and manage AI factories for enterprises sovereign AI initiatives and neocloud providers worldwide.

Headquartered in Silicon Valley California Penguin Solutions operates globally through a network of R&D manufacturing and sales locations. For nearly three decades we have operated at the intersection of memory and AI/HPC infrastructure. That engineering expertise positions us to power the next generation of AI workloads from training to inference and agentic AI at scale.

Penguin Solutions brings together differentiated infrastructure software advanced memory compute systems end-to-end services and industry-leading partner solutions in a full-stack AI factory platform designed to help customers deploy and scale AI workloads with speed and precision.

At Penguin Solutions we value ideas over hierarchy and believe in servant leadership where leaders enable teams to do their best work. We empower employees to take ownership drive innovation and grow through challenging work continuous learning and exposure to advanced AI tools and technologies. With flexibility where it matters and a strong focus on outcomes Penguin Solutions is a place to do your best work grow your career and make a meaningful impact.

Job Overview

Penguin Solutions is seeking a Senior PCB Design Layout Engineer to support the development of high-performance memory and advanced hardware products. This role focuses on complex PCB layout and design execution for high-speed digital mixed-signal and power applications including memory modules custom memory platforms and advanced system-level designs.

The ideal candidate will have strong hands-on experience with Cadence Allegro and OrCAD Capture high-speed routing controlled impedance design SI/PI design principles HDI technologies PCB stack-up development power delivery considerations and manufacturability requirements. This position requires close collaboration with hardware engineering SI/PI mechanical manufacturing test fabrication assembly and customer-facing teams to deliver reliable and manufacturable designs from concept through production release.

Responsibilities

• Own PCB design layout execution from initial floor planning through release to fabrication and assembly.
• Work closely with hardware engineers SI/PI engineers mechanical engineers PCB designers manufacturing and test teams to design new products and modify or sustain existing products.
• Create PCB component footprints per applicable IPC standards and manufacturer data sheets when needed.
• Create and review multilayer PCB stack-ups including impedance-controlled high-speed mixed-signal power and HDI designs.
• Define board outlines mechanical constraints placement keepouts route keepouts and other physical design requirements.
• Identify signal topologies and implement electrical constraints using Cadence Allegro Constraint Manager.
• Perform component placement and PCB routing including differential pairs controlled impedance lines fine-pitch BGA escape routing and tight length-matching requirements.
• Define and implement high-speed PCB design constraints for DDR PCIe CXL and other high-speed interfaces.
• Work with SI/PI engineers to support signal integrity power integrity stack-up definition impedance control routing strategies return-path planning and crosstalk mitigation.
• Support power delivery network design through power plane planning decoupling strategy and PDN-aware placement and routing.
• Collaborate with PCB fabricators on stack-up material selection impedance targets HDI construction DFM yield cost and schedule tradeoffs.
• Prepare fabrication drawings assembly drawings Gerber files ODB/IPC-2581 files as required and complete PCB release packages.
• Lead placement reviews routing reviews post-layout reviews and DFM reviews and support schematic and manufacturing readiness reviews.
• Mentor junior PCB designers and help improve PCB design standards library practices constraint methodology and release processes.
• Stay current with industry standards PCB fabrication technologies design tools and best practices and recommend improvements where appropriate.

Qualifications

• Bachelors degree in Electrical Engineering Electronics or related technical discipline preferred; equivalent experience will be considered. Masters degree is a plus.
• 8 years of PCB design/layout experience for high-speed digital mixed-signal and power designs.
• 5 years of hands-on experience with Cadence Allegro and OrCAD Capture.
• Strong experience with high-speed digital design practices controlled impedance routing differential pair routing length matching timing/skew management topology implementation return paths and crosstalk considerations.
• Experience with complex multilayer PCBs preferably 12-24 layers including HDI blind/buried vias microvias via-in-pad sequential lamination fine-pitch BGAs and advanced fabrication constraints.
• Experience with power supply circuits analog circuits mixed-signal layout practices and power delivery considerations.
• Ability to read interpret and apply component manufacturer data sheets reference designs layout guidelines and fabrication requirements.
• Working knowledge of JEDEC DDR4 and DDR5 standards is highly preferred. Experience with DDR3 MRDIMM CXL PCIe or other high-speed memory interfaces is a plus.
• Experience designing memory modules server boards accelerator cards storage products or high-speed embedded systems is a plus.
• Ability to interface with customers and internal stakeholders to understand requirements and translate them into manufacturable PCB designs.
• Self-starter with strong organizational skills attention to detail ownership mindset and excellent verbal and written communication skills.
• Ability to identify areas of innovation in memory design. Experience with invention disclosure or patent processes is a plus.

Location

This position can sit remotely in the Pacific Time Zone with preference being in the state of California. There are physical locations in Newark CA and Irvine CA should you prefer a Hybrid or Onsite model.

Travel

None anticipated

Compensation & Benefits

The base pay range that the Company reasonably expects to pay for this position in California is $; the pay ultimately offered may vary based on business considerations including job-related knowledge skills experience and position is bonus-eligible and there are medical dental and vision benefits available. There is a 401k saving plan and other benefits such as Paid Time Off Life Insurance and an Employee Assistance Plan.

Inclusion & Belonging Statement

We are committed to creating an inclusive environment that embraces differences and fosters belonging for all.

Equal Opportunity Statement

We are an Affirmative Action/Equal Opportunity Employer and are strongly committed to policies that provide equal employment opportunity to all qualified persons without regard to age national origin race ethnicity creed gender disability veteran status or any other characteristic protected by law.