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Senior or Principal PLL Design Engineer
Job Location:
Job Location:
San Jose, CA - USA
Monthly Salary:
Not provided by the employer
Monthly Salary:
Posted:
13 June 2026 (30+ days ago)
Posted:
Application Deadline:
10 September 2026
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Senior to Principal PLL Design Engineer roles
Locations: Irvine CA or San Jose CA
About the job
Are you a PLL Design Engineer who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI We are looking for a High-Speed CMOS PLL Analog Design Engineer who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers high-speed SerDes and ADC/DAC systems. Candidate will have the opportunity to architect and design PLLs for next generation transceivers.
What You Will Do
Understand trade-offs between different PLL topologies (e.g. integer-N fractional-N all-digital/ADPLL) to meet specifications for power area jitter and frequency range
Architect design and simulate analog/mixed-signal PLL building blocks (VCOs charge pumps dividers PFDs Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre
Address challenges in advanced node technologies such as self-heating electromigration voltage-controlled oscillator (VCO) linearization and device-level noise optimization
Supervise and verify layouts produced by layout engineers to ensure floorplanning matching and parasitic minimization using advanced node technologies
Be responsible for PLL bring up in the lab conducting performance characterization using state-of-the-art lab equipment
Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies
What You Will Bring
Masters degree and/or PhD in Electrical Engineering or related fields with 5 years of relevant experience in PLL design and production level tape-out experience.
Must have extensive experience with advanced node technologies (16nm/12nm 7nm 5nm 3nm 2nm processes)
Deep understanding of phase noise analysis VCO design LDOs and supporting circuitry associated with PLLs
Proficient in cadence virtuoso electromagnetic simulator (e.g. EMX/HFSS) and MATLAB for system-level modelling
Strong communication and documentation skills
Annual Base Salary Range: $150000 - $250000 (The final offer will be determined based on job-related skills experience qualifications and location.)
Locations: Irvine CA or San Jose CA
About the job
Are you a PLL Design Engineer who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI We are looking for a High-Speed CMOS PLL Analog Design Engineer who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers high-speed SerDes and ADC/DAC systems. Candidate will have the opportunity to architect and design PLLs for next generation transceivers.
What You Will Do
Understand trade-offs between different PLL topologies (e.g. integer-N fractional-N all-digital/ADPLL) to meet specifications for power area jitter and frequency range
Architect design and simulate analog/mixed-signal PLL building blocks (VCOs charge pumps dividers PFDs Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre
Address challenges in advanced node technologies such as self-heating electromigration voltage-controlled oscillator (VCO) linearization and device-level noise optimization
Supervise and verify layouts produced by layout engineers to ensure floorplanning matching and parasitic minimization using advanced node technologies
Be responsible for PLL bring up in the lab conducting performance characterization using state-of-the-art lab equipment
Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies
What You Will Bring
Masters degree and/or PhD in Electrical Engineering or related fields with 5 years of relevant experience in PLL design and production level tape-out experience.
Must have extensive experience with advanced node technologies (16nm/12nm 7nm 5nm 3nm 2nm processes)
Deep understanding of phase noise analysis VCO design LDOs and supporting circuitry associated with PLLs
Proficient in cadence virtuoso electromagnetic simulator (e.g. EMX/HFSS) and MATLAB for system-level modelling
Strong communication and documentation skills
Annual Base Salary Range: $150000 - $250000 (The final offer will be determined based on job-related skills experience qualifications and location.)
Javier Leon
Talent Acquisition
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Talent Acquisition
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Required Experience:
Staff IC
