Senior Engineer II Layout

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Job Description:

Join the Layout Engineering team as a Senior Engineer II-Layout supporting highly complex semiconductor physical layout integration extraction verification manufacturability reliability and design-closure challenges. This role is best suited for candidates with 7.510 years of relevant experience in semiconductor custom or physical layout analog digital mixed-signal memory IO ASIC SoC physical verification or a closely related area.

In this role you will integrate highly complex layout circuit technology reliability manufacturing risk and cross-functional technical decisions within approved scope partner with circuit design physical design verification technology CAD product test manufacturing quality reliability and leadership teams and help deliver robust physical implementation verification closure manufacturability reliability and product outcomes.

Responsibilities:

• Define and execute highly complex layout architectures floorplans device structures interconnect power distribution matching shielding extraction and verification strategies within approved scope.
• Integrate circuit interface technology performance power area reliability manufacturability design-rule and schedule requirements.
• Resolve critical layout connectivity parasitic matching coupling electromigration physical-verification integration or tapeout-readiness issues through structured root-cause leadership.
• Evaluate evidence quality uncertainty risks dependencies waivers and alternative approaches; communicate decision-ready recommendations.
• Coordinate cross-functional technical decisions and layout closure within approved scope.
• Establish reusable layout structures automation verification extraction design-rule and release practices.
• Review decision-ready requirements floorplans layouts extracted results reports waivers defects and release evidence.
• Provide advanced technical guidance while organizational authority remains separately approved.

Requirements/Qualifications:

Minimum qualifications: Bachelors degree in Electrical Engineering Electronics Engineering Computer Engineering Physics or a related field with 7.510 years of relevant experience in semiconductor layout custom physical design analog digital mixed-signal memory IO ASIC or SoC layout floorplanning device placement routing extraction physical verification or closely related equivalent experience.

Qualified candidates should demonstrate analytical thinking semiconductor-layout judgment geometric and spatial reasoning structured problem solving verification discipline root-cause analysis technical documentation evidence-based communication cross-functional collaboration quality focus and the ability to work with complex design rules schematics devices interconnect parasitics reliability manufacturing and signoff information.

Successful candidates are expected to demonstrate:

• Employment stability reliability and sustained accountability in prior roles.
• Effective teamwork and cross-functional collaboration.
• Integrity and accuracy in representing qualifications experience and credentials.

Preferred Qualifications:

• Experience with semiconductor custom analog digital mixed-signal memory IO pad RF ASIC or SoC layout.
• Experience with floorplanning device placement routing matching shielding power distribution extraction DRC LVS ERC antenna density reliability or physical-verification closure.
• Experience with layout and physical-verification tools scripting automation process-design kits advanced process nodes or design-for-manufacturing methods.
• Masters degree in Electrical Engineering Electronics Engineering Computer Engineering Physics or a related field.

Travel Time:

0% - 25%

Physical Attributes:

Feeling Handling Hearing Seeing Talking Works Alone Works Around Others

Physical Requirements:

70% sitting 15% standing 15% walking; 100% in doors; Usual business hours.

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay restricted stock units and quarterly bonus addition to these components our package includes health benefits that begin day one retirement savings plans and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position which could be performed in the US is $70304-$205000.*

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex gender identity sexual orientation race color religion national origin disability protected Veteran status age or any other characteristic protected by law.

For more information on applicable equal employment regulations please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.

To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.