Scientist, Software Engineering

Job Title: Scientist Software Engineering (FPGA Design)

Job ID: Req ID 47447

Job Location: Salt Lake City UT

Job Schedule: 9/80: Employees work 9 out of every 14 days - totaling 80 hours worked - and have every other Friday off

Job Description:

We are seeking a talented FPGA Design Engineer with industry experience in wireless digital communications networking and/or cryptography to join our team developing advanced wireless digital communication and electronic warfare systems. This role spans the full FPGA development lifecycle including bids and proposals requirements definition specification development and maintenance RTL design and coding simulation synthesis place and route verification through simulation and unit testing system integration and ongoing support. The engineer will participate in code and design reviews and ensure that high-speed digital FPGA designs meet written specifications within a DoW process-controlled work environment. The ideal candidate enjoys challenging technical work and thrives both as part of a talented engineering team and as an individual contributor.

Essential Functions:

Areas of desired technical experience or education include:

• Networking protocols
• Cryptographic Algorithms
• Industry standard interfaces (e.g.. 10/100/1000 Ethernet SPI UART SDRAM DDR3 JESD PCIe etc.).
• FPGA verification through simulation and unit testing

Qualifications:

• Bachelors Degree and a minimum of 12 years of prior relevant experience. Graduate Degree and a minimum of 10 years of prior related lieu of a degree minimum of 16 years of prior related experience.12 years FPGA design experience
• Experience leading teams of technical employees
• Must be able to secure or maintain a U.S. Department of Defense security clearance.

Preferred Additional Skills:

• Bachelors (Masters preferred) degree in Computer Engineering or Electrical Engineering.
• Experience in VHDL (preferred) or Verilog UVM and SystemVerilog development languages.
• Experience in simulation synthesis and placement software tools such as ModelSim Synplicity AMD Vivado / ISE and/or Altera Quartus development tool sets.
• Experience witth HLS (High-Level Synthesis)
• Experience with timing closure in large FPGAs.
• Experience in laboratory debug techniques using digital scopes logic analyzers BERTS and other complex measurement devices.
• FPGA Design using High-speed serial interfaces (3 Gbps)
• Familiarity with code revision management tools (preference for Git/Bitbucket and/or Clearcase).
• Familiarity with C/C/C# is a plus.
• Active U.S. Department of Defense security clearance is preferable.

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