Principal Lead DSP & Systems Architect — Ultra High-Speed SerDes
Job Location:
Milpitas, CA - USA
Monthly Salary:
Posted:
Application Deadline:
Vacancies:
Job Summary
About the Company
Omni Design Technologies provides high-performance ultra-low power IP solutions across advanced CMOS nodes enabling differentiated SoC architectures for AI/ML accelerators hyperscale datacenter interconnects optical networks and next-generation wireline platforms. We partner with market leaders globally and are scaling rapidly and are seeking senior technical leadership to define the next generation of ultra high-speed SerDes IP at 448G and beyond.
Job Description
We are seeking a Principal / Lead DSP & Systems Architect to own the architectural direction of ultra high-speed SerDes platforms targeting 448G per lane and emerging post-448G standards spanning both electrical (chip-to-chip backplane copper cable) and optical (IM-DD and coherent) interfaces. This individual will drive end-to-end link architecture DSP algorithm design and ADC/DAC-based transceiver partitioning serving as the primary technical interface with strategic customers and standards bodies.
The ideal candidate combines deep expertise in high-speed link theory advanced equalization and FEC PAM/multi-level and coherent signaling and hardware-aware DSP implementation with a track record of delivering SerDes IP into silicon at the bleeding edge of the wireline and optical roadmap.
Architecture & Roadmap: Define DSP and system architecture for 448G and post-448G SerDes IP across electrical and optical interfaces including ADC/DAC-based transceiver partitioning modulation choice (PAM4/PAM6 IM-DD coherent) and FEC strategy and shape long-term roadmap toward 1.6T and 3.2T link aggregates.
Customer & Standards Engagement: Lead technical engagement with hyperscale AI accelerator and optical module customers; represent the company in OIF CEI IEEE 802.3 and related standards activities.
End-to-End Link Modeling: Build and maintain MATLAB/Python models of the full link across electrical and optical media: channel response (backplane copper cable chip-to-chip fiber) TX/RX impairments jitter (RJ/DJ/BUJ) crosstalk reflections optical impairments (CD PMD laser phase noise optical SNR) ADC/DAC quantization and FEC performance under realistic BER/FLR targets.
DSP Algorithm Architecture: Own the DSP pipeline across electrical and optical paths FFE DFE MLSE/MLSD CTLE-DSP partitioning adaptive equalization (LMS sign-sign LMS blind adaptation) timing recovery and CDR baseline wander correction IQ/skew calibration PAM demapping and integration with KP4 / concatenated / soft-decision FEC. For optical links additionally drive chromatic dispersion (CD) compensation polarization demultiplexing carrier phase and frequency recovery and nonlinear compensation.
Mixed-Signal Co-Design: Drive ADC/DAC architectural decisions sample rate resolution (ENOB) time-interleaving calibration strategy and align analog front-end CTLE and clocking specs with DSP performance budgets.
Fixed-Point & Implementation Trade-offs: Drive wordlength optimization parallelism and pipelining strategies for multi-hundred-GSps datapaths and float-to-fixed methodology to balance BER performance area and pJ/bit power efficiency.
Specifications & Cross-Domain Integration: Generate block-level specs for DSP datapaths FEC calibration ADC/DAC AFE and clocking; align decisions across digital mixed-signal packaging and SI/PI domains.
DSP-to-RTL Handoff: Translate DSP reference models into hardware-friendly architectures with bit-true/cycle-accurate alignment and partner with RTL and verification teams on micro-architecture latency and memory trade-offs.
Silicon Bring-up & Validation: Partner with validation and lab teams to correlate post-silicon BER eye and link-training results with modeled assumptions; define KPIs (BER FLR link margin power latency) and debug methodologies.
Mentorship & Thought Leadership: Guide DSP systems and hardware engineers; develop reusable models and best practices; contribute to architecture reviews IP innovation strategy and customer-facing technical engagements.
- Graduate degree in EE Communications or Signal Processing; PhD strongly preferred.
- 10 years in high-speed SerDes or wireline/optical link DSP/systems architecture with direct exposure to 112G/224G silicon and a clear path into 448G and beyond across electrical and optical interfaces.
- Proven ownership of end-to-end link budgets with cascaded impairment analysis across channel (electrical and/or optical) AFE ADC/DAC DSP and FEC.
- Deep expertise in: PAM4/PAM6 and coherent wireline/optical signaling; advanced equalization (FFE DFE MLSE/MLSD Tomlinson-Harashima); optical DSP (CD/PMD compensation polarization recovery carrier phase/frequency recovery) for candidates with optical exposure; adaptive algorithms and link training; KP4 and soft-decision FEC; high-speed ADC/DAC architectures (time-interleaved calibration ENOB-driven design); CDR and timing recovery at multi-hundred-Gbaud rates; jitter/crosstalk/SI and optical impairment modeling; fixed-point DSP and bit-true modeling; MATLAB/Python link simulation; DSP-to-RTL methodology.
- Familiarity with OIF CEI (CEI-224G CEI-448G) IEEE 802.3 high-speed Ethernet and relevant optical standards (e.g. OIF coherent agreements IEEE 802.3 optical PHYs).
- Track record of defining specs consumed by RTL DSP mixed-signal verification and validation teams.
- Strong communication skills with VP- and CTO-level stakeholders at hyperscale and module customers.
- Highly competitive compensation performance incentives and substantial technical influence.
- Direct ownership of DSP and systems architecture for SerDes IP at the bleeding edge of the wireline and optical roadmap.
- Strategic relationships with top-tier hyperscale AI and optical customers.
- A technical culture that values rigor clarity and architectural craftsmanship.
Required Experience:
Staff IC
About Company
We are a leading provider of high-performance, ultra low power data converter IP for semiconductor applications in 5G, AI, LiDAR, and more.
