Principal Engineer, SOC Integration

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Advancing the Worlds Technology Together

Our technology solutions power the tools you use every day--including smartphones electric vehicles hyperscale data centers IoT devices and so much more. Here youll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of whats possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. Were dedicated to empowering people to be their true selves. Together were building a better tomorrow for our employees customers partners and communities.

What Youll Do

TheDRAM Development Lab(DDL) is part of Samsungs Memory Business Unit the industrys technology and volume leader in DRAM HBM and NAND Flash. DDLs vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions. We are an integral part of Samsungs strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

Come join the team as a Principal Engineer SOC Integration that is creating new computing system architectures needed to support emerging machine learning applications data analytics and edge computing. Youll focus on enhancement of memory and storage capability by developing prototype and production controllers.

Location: Daily onsite presence at our San Jose office/headquarters in alignment with our Flexible Work policy

Job ID: 42979

• Own the integration of SoCs with multiple high speed interfaces
• Reviews 3^rd party IPs including ARM cores DDR controller and UCIe PHY and
• Responsible for integrating the third part IPs with system bus peripherals and CPU cores.
• Work closely with architects and verification engineers to ensure sound design at SoC level.
• Work with physical designers on timing constraints synthesis DFT insertion and static timing analysis

What You Bring

• BS in Computer/Electrical Engineering or Computer Science with 20 years of experience or a MS with 18 years of experience.
• Hands on knowledge & experience in ASIC design flow from design to tape out.
• Experience in the commercial IPs such as UCIe CPU Ethernet and DDR interfaces.
• Good understanding of PPA (performance power and area) trade-offs.
• Experience in SoC level synthesis timing analysis lint check CDC checks.
• Good knowledge and experience in AMBA bus fabric ARM CPU cores and ARM Co-sight debug features.
• Self-motivated problem-solver with an ability to work well in a team.
• Youre inclusive adapting your style to the situation and diverse global norms of our people.
• An avid learner you approach challenges with curiosity and resilience seeking data to help build understanding.
• Youre collaborative building relationships humbly offering support and openly welcoming approaches.
• Innovative and creative you proactively explore new ideas and adapt quickly to change.

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