Physical Design Engineer

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APPLE INC has the following available in San Diego California. Build full chip clock trees perform specification generation clock planning involving design and construction of recombinant networks. Automate clock tree specification generation for clock construction and distribution across the dies to meet all the clock tress specifications latency and power. Work with logic design team to understand partition architecture and drive physical aspects early in the design cycle. Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. Conduct timing physical and electrical verification and drive the signoff closure for the partitions. Resolve design and flow issues related to physical design identify potential solutions and drive execution. 40 hours/week. At Apple base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175000 - $263300/yr and your base pay will depend on your skills qualifications experience and location. nnPAY u0026 BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apples discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards and can purchase Apple stock at a discount if voluntarily participating in Apples Employee Stock Purchase Plan. Youll also receive benefits including: Comprehensive medical and dental coverage retirement benefits a range of discounted products and free services and for formal education related to advancing your career at Apple reimbursement for certain educational expenses including tuition. Additionally this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: Apple benefit compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Masters degree or foreign equivalent in Computer Engineering Electrical Engineering related field and 2 years of experience in the job offered or related and/or education must include:nBuilding clock networks for high-performance CPU cores ensuring minimal latency on the latest interconnect delays parasitics and coupling and understanding the impact on system interconnect wire delays for optimal dynamic power with FinFET and GAA standard cell technologies to perform physical design achieving best performance power and full chip clock trees spec generation clock planning involving design and construction of recombinant clock tree spec generation for clock construction and distribution across the dies to meet all the clock tress specs latency and industry standard EDA tools including Synopsys or Cadence with the understanding of the algorithms driving static timing analysis physical design verification analysis and place and route methodology in achieving best PPA.

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