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Interface Design Verification Engineer
Job Location:
Job Location:
San Jose, CA - USA
Monthly Salary:
Not provided by the employer
Monthly Salary:
Posted:
1 July 2026 (30+ days ago)
Posted:
Application Deadline:
28 September 2026
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Job Title: Interface Design Verification Engineer
Location: San Jose CA
Job Description:
Looking for engineers with strong protocol expertise to verify industry-standard interface IPs such as PCIe DDR Ethernet USB etc.
Key Responsibilities:
- Verify interface IPs for protocol compliance and robustness
- Develop UVM testbenches using VIPs
- Execute corner-case and stress testing
- Analyze protocol-level failures and debug issues
- Work with design teams to ensure spec compliance
Required Skills:
- Strong knowledge of standard protocols (PCIe/DDR/USB/Ethernet)
- Expertise in SystemVerilog UVM and VIP integration
- Experience with protocol analyzers and debugging
Good to Have:
- Experience in high-speed interfaces
- Understanding of PHY-layer concepts
