Hardware & Silicon Validation Principal Engineer

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

Lead electrical characterization compliance and debug for SerDes IP targeting Ethernet IEEE 802.3ck/dj and PCIe Gen5/Gen6 standards at 112G/224G data rates.
Develop and implement automated validation methodologies regression frameworks and compliance test plans for SerDes interfaces across multiple product lines.
Drive signal integrity analysis and optimization for high-speed channels including correlation between pre-silicon modeling simulation and lab measurements.
Own the end-to-end SerDes validation strategy for assigned product programs from test plan development through production readiness sign-off.
Provide technical leadership and applications engineering support to strategic customers including on-site debug and performance optimization.
Define and manage equipment CAPEX plans for advanced test equipment; ensure measurement infrastructure readiness for current and next-generation SerDes IP.
Mentor and develop staff-level and junior engineers in high-speed signal integrity measurement techniques debug methodologies and test automation best practices.
Collaborate closely with SerDes design architecture and product engineering teams to drive silicon quality from early bring-up through volume production.
Contribute to high-speed board design reviews extraction and characterization; partner with internal tools teams to build robust test infrastructure.
Author technical collateral including validation reports application notes and best-known-methods documentation for internal and customer use.
Represent Marvell in industry forums and customer technical reviews; contribute to standards awareness for IEEE 802.3 and PCI-SIG specifications.

What Were Looking For

Bachelors degree in Computer Science Electrical Engineering or a related field with 8 years of relevant industry experience; or Masters degree and/or PhD in Computer Science Electrical Engineering or a related discipline with 5 years of professional experience.
57 years of direct experience in SerDes characterization design or signal integrity engineering.
Deep expertise in Ethernet IEEE 802.3ck/dj electrical compliance and validation and/or PCIe Gen5/Gen6 specifications.
Strong knowledge of signal integrity principles channel modeling S-parameter analysis equalization architectures (CTLE DFE FFE) and board-level design for high-speed interfaces.
In-depth working knowledge of test equipment used for SerDes characterization: real-time and sampling oscilloscopes BERTs vector network analyzers pattern generators and protocol analyzers.
Strong proficiency in Python scripting for test automation data analysis and regression infrastructure development.
Demonstrated ability to lead technical projects and mentor engineers.
Experience correlating pre-silicon simulations with post-silicon measurements and driving closure on discrepancies.
Experience with high-speed PCB design signal integrity simulation tools (HFSS ADS Sigrity or equivalent) and channel extraction methodologies is preferred
Active participation or familiarity with IEEE 802.3 or PCI-SIG standards committees is preferred.
Critical thinking and problem-solving attitude with ownership of the groups results.
Excellent verbal and written communication skills; ability to present technical content to customers and executive leadership.

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.