Hardware Engineer Electrical Engineer


Job Location:

Melbourne, FL - USA

Monthly Salary: Not Disclosed
Posted on: 1 hour ago
Vacancies: 1 Vacancy

Job Summary

Position: Hardware Engineer/ Electrical Engineer (DO-254)

Location: Melbourne FL (Onsite)

Long Term Contract

Expert level verification engineer with strong System Verilog and UVM experience. As an alternative to SystemVerilog/UVM we are open to candidates with a verification background in lab testing and/or design verification testing. Experience with design on Xilinx products would be a strong plus.

Required Skills:

  • Expert level verification engineer with strong System Verilog and/ or UVM experience
  • FPGA verification in lab testing and/or Hardware FPGA design verification testing
  • Experience with design on Xilinx products would be a strong plus
  • expected to communicate effectively with emerging engineers at the India GETC I site and provide both technical and process (DO-254) guidance to the verification team.

Core Responsibilities

  • RTL Design & Simulation: Develop code and testbenches using VHDL Verilog and SystemVerilog.
  • Verification: Create UVM constrained random environments and conduct static timing linting and clock-domain-crossing (CDC) analyses.
  • DO-254 Certification: Create artifacts required for Airborne Electronic Hardware (AEH) DAL-A certification and participate in FAA SOI audits.
  • Hardware Lifecycle: Handle requirements capture decomposition architecture development synthesis and placement & routing.

Key Qualifications

  • Experience: Substantial hands-on FPGA or ASIC development experience (typically 5 years for a senior designation).
  • Education: Degree in a STEM (Science Technology Engineering Mathematics) field.
  • Avionics Knowledge: Familiarity with design assurance standards (DO-254) is highly preferred.
Position: Hardware Engineer/ Electrical Engineer (DO-254) Location: Melbourne FL (Onsite) Long Term Contract Expert level verification engineer with strong System Verilog and UVM experience. As an alternative to SystemVerilog/UVM we are open to candidates with a verification background in lab ...