Front End Design Engineer

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APPLE INC has the following available in Austin Texas. Convert RTL designs into netlists using industry-standard RTL synthesis tools. Optimize power performance and area by experimenting with synthesis recipes and enhancing existing synthesis methodologies. Understand RTL code written in Verilog and SystemVerilog languages correlate it to gate-level circuits and guide the development of optimal RTL solutions. Perform Clock and Reset Domain Crossing (CDCRDC) checks to ensure the designs robustness against metastability-related problems and lint checks. Perform logical equivalence checks to ensure correctness of the generated netlist and support ECO generation activities. Perform static timing analysis (STA) to identify critical paths in the design then propose solutions spanning both physical implementation and microarchitectural optimizations. Analyze RTL simulation waveforms using industry standard simulator tools to understand the designs intent and common signal activity pattern. Lint checks to ensure the overall quality of RTL code. Collaborate effectively with internal Ru0026D teams. 40 hours/week.

Masters degree or foreign equivalent in Electrical and Computer Engineering Electrical Engineering or a related field and 1 year of experience in the job offered or related and/or education must include:nnSynthesizing RTL designs using Design Compiler/Genus into netlistnUnderstanding RTL and make RTL updates for PPAnCreating unit testbench to verify RTL updatesnWorking with simulation waveform to understand design intentnPerforming Static Timing Analysis (STA) and achieving timing closurenPerforming Lint checks to ensure RTL qualitynPerforming Clock Domain Crossing checks (CDC)nPerforming Reset Domain Crossing Checks (RDC)

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