Emulation Engineer
Cupertino, CA - USA
Job Summary
As a member of SOC emulation team candidate will be involved in:n-Support multiple Emulation environments using the latest emulation techniques:- C/C DPI Transactors SV assertions Coverage Power Estimation SpeedBridges Accelerated UVM Testbenches.n-SoC bringup on emulation root cause failing SoC/Processor tests and emulator environment issuesn-Strong design debug communication and teamwork skills are essentialn-Work with the leading emulation vendors to debug issues.n-This role requires close collaboration with Design DV Power Silicon Validation Performance and Software teams.
Bachelors degree and a minimum of 10 years relevant industry experience.
Experience with Verilog VHDL designnExperience with C/C and System Verilog Design Verification environmentsnExperience with waveform debug toolsnExperience in writing Synthesize-able SystemVerilog/Verilog code and SystemVerilog assertionsnExperience on any Scripting (Perl/Python/TCL/Makefile)nExcellent analytical and debug skillsnEmulation experience on available platforms-Palladium Veloce or Zebu including compilation debug performance and throughput tuning is a strong plusnExperience with Serial/High-Speed Protocols (PCIE USB Display CIO) UVM Acceleration is communication skills and ability to work as a team.
Required Experience:
IC
About Company
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