Digital Logic + Design Verification Graduate Co-Op Program (US Fall 2026)

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

• Contribute to RTL design and implementation of digital logic blocks for ASICs/SoCs
• Support micro-architecture development design specification and implementation
• Assist with synthesis timing analysis and design reviews
• Collaborate with verification and physical design teams to ensure design quality

• Develop and execute verification test plans for digital and SoC designs
• Build simulation environments testbenches and verification components
• Debug simulation failures and analyze coverage
• Work closely with design engineers to ensure functional correctness and performance

• Use industry-standard tools such as Verilog/SystemVerilog UVM and scripting languages
• Automate workflows and analyze data using Python or similar tools
• Support end-to-end chip development from architecture through validation
• Collaborate with global engineering teams on leading-edge semiconductor products

What Were Looking For

• Currently enrolled in a Masters or PhD program in Electrical Engineering Computer Engineering or a related field
• Strong foundation in digital logic design and computer architecture
• Familiarity with HDL languages such as Verilog or SystemVerilog
• Strong problem-solving analytical and communication skills

• Exposure to UVM or formal verification methodologies
• Experience with RTL design simulation or FPGA-based projects
• Knowledge of scripting languages (Python Perl TCL or shell)
• Familiarity with SoC design concepts or high-speed interfaces (e.g. PCIe DDR)
• Prior internship or academic project experience in digital design or verification

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.