Design Verification Engineer Remote Contract opportunity

Role Design Verification Engineer

Location Remote (must be aligned with PST time zone)

Duration- Contract opportunity

Job Description and other details

We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality performance and robustness of our custom silicon designs. You will help define the verification approach contribute to methodology and work closely with architecture RTL design DFT firmware physical design and silicon validation engineers. This is a hands-on role with high ownership deep technical engagement and the opportunity to shape first-generation silicon.

Qualifications

• B.S. or M.S. in Electrical Engineering Computer Engineering or related field.
• 3 years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog digital logic and hardware verification flows.
• Proficiency with a simulation (VCS Xcelium Questa) waveform debug (Verdi SimVision) and coverage tool.
• Experience with test planning testbench development constrained-random testing and coverage analysis.
• Familiarity with a scripting language (ex: Python Perl TCL) and revision control system (ex: Git).

Responsibilities

• Develop and execute verification plans for block-level subsystem-level and full-chip environments.
• Build SystemVerilog/UVM test benches including agents monitors scoreboards checkers and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality corner cases and stress scenarios.
• Run simulations triage failures drive root-cause analysis and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage code coverage assertion coverage and ensure coverage closure for sign-off.
• Manage regression testing simulation farms and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews and microarchitecture discussions.