CPU Full-chip Physical Integration Engineer

Imagine what you could do here. At Apple new ideas have a way of becoming extraordinary products services and customer experiences very quickly. Bring passion and dedication to your job and theres no telling what you could accomplish. Dynamic hard-working people and inspiring innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! nnApples Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.

As a Full Chip Integration Engineer you will be participating in the physical design integration and verification of high performance low power processor development. nn Full chip floorplan area optimizations block partitioning and pin placementsn Own chip level place and route (PnR) final CPU layout database construction and verification (PDV)n Develop and validate Power Grid including routability analysisn Drive custom layout integration block and full-chip level EM/IR electrical verification/analysis as well as formal verificationn Work with the implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeoutn Work with the SOC team to meet IP technical and delivery requirementsn Participate in establishing CAD and physical design methodologies and flow development for chip integration and analysisn Scripting to automate tasks and improve debug efficiency

Minimum BS and 10 years of relevant industry experiencenExperience with scripting in Perl or TCL

Knowledge of industrial standards and practices in Physical Design including Floorplanning Partitioning Budgeting Place and Route and Physical VerificationnExperience in developing and implementing Power Grid and Clock specificationsnSolid knowledge of Low Power Design Physical Construction Integration EMIR (Drop/Noise) SIGEM Analysis Formal Verification Physical PDV DRC/LVS Verification and DFMnSolid understanding of verification tools such as Conformal LP LEC RedHawk CalibrenSolid understanding of CMOS circuit design. Layout design background is a plusnWorking knowledge of Extraction and STA methodology and toolsnWorking knowledge of Computer ArchitecturenAbility to work well in a team being an excellent problem solver and self motivated