CPU Core Design Verification Test Generator Lead

Tenstorrent is leading the industry on cutting-edge AI technology revolutionizing performance expectations ease of use and cost efficiency. With AI redefining the computing paradigm solutions must evolve to unify innovations in software models compilers platforms networking and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration curiosity and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

At Tenstorrent we build open state of the art compute for real workloads and real developers.

You will own CPU focused test generator development and verification strategy shaping how our out-of-order RISC-V CPUs are validated against complex ISA and microarchitectural behavior.

This role is hybrid based out of Austin TX or Santa Clara CA.

We welcome candidates at various experience levels for this role. During the interview process candidates will be assessed for the appropriate level and offers will align with that level which may differ from the one in this posting.

Who You Are

• You bring 8 years in CPU design verification test generation or closely related CPU validation work.
• You have led development of test generators for x86 ARM or RISC-V ISA environments.
• You understand CPU ISA behavior privileged architecture and high-performance out-of-order CPU microarchitecture.
• You are comfortable building tools stimulus and automation that scale verification across large CPU programs.
• You communicate clearly across design DV architecture emulation and post-silicon teams.

What We Need

• Lead development of CPU core-level test generators for high-performance out-of-order RISC-V cores.
• Own generator strategy infrastructure and methodology for ISA and microarchitectural verification in both pre-silicon and post-silicon
• Develop directed and randomized stimulus that targets architectural corner cases instruction interactions and complex CPU behavior.
• Support RISC-V certification work including test content compliance flows debug and closure.
• Guide a small team of 4-5 engineers while staying hands-on with implementation debug and verification execution.

What You Will Learn

• How Tenstorrent designs and validates high-performance RISC-V CPU cores and clusters.
• Techniques for scaling CPU test generator infrastructure across core cluster and chip-level environments.
• Ways to apply ISA-driven stimulus to complex CPU verification and debug workflows.
• Techniques for supporting RISC-V certification alongside internal verification requirements.
• How to scale coverage debug and generator methodology across multiple CPU programs within Tenstorrents broader compute roadmap.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws including those codified in the U.S. Export Administration Regulations (EAR) the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1 E1 and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information systems or technologies subject to these laws the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws any offer of employment will be rescinded.