Cellular ASIC Design Engineer – Protocols

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Were looking for a Cellular ASIC Design Engineer where you will architect and implement protocol processing hardware for next-generation wireless SoCs. You will own the full lifecycle from early architectural exploration and HW/SW partitioning through RTL implementation to silicon bring-up and lab validation. You will collaborate closely with software firmware and verification teams to deliver hardware that balances performance flexibility and power efficiency.

Micro-architecture and RTL implementation for cellular protocol and optimize pipelining architectures to improve performance latency optimization and quality of service (QoS) HW/FW/SW partitioning for protocol processing architectural prototypes to validate design decisions up and debug hardware in the lab.

BS and a minimum of 10 years relevant industry -on expertise in SystemVerilog and in with synthesis and timing analysis with low-power design with AMBA bus protocols (AXI AHB) or similar on-chip in designing and optimizing scheduling and QoS mechanisms.

MS or PhD in Computer Engineering or Electrical of cellular MAC WiFi MAC or other data-link layer (L2) grasp of IP and TCP/UDP in network infrastructure architecture (e.g. routers access points switches).nExperience with packet buffering queuing and of security algorithms (AES or similar).nExperienced with scheduling and arbitration designs for memory architectural models in C/C or SystemC.