ASIC Layout Designer

Overview

Tektronix is seeking a hard-working and dedicated ASIC Layout Design Engineer. We value inquisitive problem solvers who are motivated and this role you will be responsible for block and chip-level layout of high-performance RF Analog ASICs collaborating closely with design engineers and layout teams.

Your mission: ensure outstanding product flow from development to mass production meeting all manufacturing quality and cost goals. Once in production your contributions to test time reduction diagnostics and yield improvement will be critical.

Ready for your next challenge Tektronix may be the place for you!

Key Responsibilities

• Layout of cells blocks and chips in CMOS BiCMOS and Bipolar processes
• Chip-level assembly verification and debugging
• Planning and managing layout teams including contractors and teammates
• Layout tool development and training
• Troubleshooting layout software and PDKs
• Project database management
• Driving top-down abstraction and black-box methodology

Qualifications

• Minimum 7 years of experience in RF/Analog/Mixed Signal layout design
• Proficient in broadband RF/high-speed layout sensitive RF analog matching and parasitic minimization
• Experience with PDKs and multiple foundry processes
• Skilled in efficient chip block and cell floor planning and signal path optimization
• Strong understanding of: Electromigration Well-proximity and length-of-diffusion effects Common-centroid matching Differential pairs Current mirrors
• Comfortable with arrays mirrored and quadrature layouts
• Expertise in RF analog and digital routing physical verification and database management
• Familiarity with layout of: DAC/ADC Broadband amplifiers VGAs Regulators VCOs PLLs dividers Samplers Bandgaps Charge pumps IO/ESD structures
• Strong understanding of RF analog digital and mixed-signal fundamentals
• Technical Skills

CAD Tools:

• Cadence Virtuoso Schematic L Layout L and XL
• Physical Verification & Extraction: Cadence Assura PVS Pegasus Siemens tool suits including Calibre customIC Solido Aprisa and Questa
• Design Management: SVN SOS Synchronicity IC Manage (or similar)
• Programming/Scripting:
• Skill Python Ruby Shell scripting
• P-Cell development
• Bonus:
• Knowledge of Cadence Allegro PCB Design
• Soft Skills
• Excellent communication and interpersonal skills
• Strong teamwork and leadership capabilities
• Ability to mentor and collaborate across teams