Architecture & Performance Modelling Engineer

Job Description:

Our client is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers delivering Faster AI. Todays AI performance is frequently limited by communication bottlenecks.

Our client introduces multiple industry-first innovations across silicon packaging software and systems to deliver sharp improvement in performance and greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference.

The companys solutions and value proposition are validated by leading hyperscalers.

Our client has raised over $200M including a recent Series A round. The company is led by a team of Silicon Valley executives who have delivered multiple product lines and led multiple companies to billion-dollar exits.

The company has a world-class engineering team with decades of experience in state-of-the-art silicon packaging optics software and systems.

Position Overview

We are seeking a highly skilled and visionary Performance Modeling Engineer to drive the definition development and application of our clients AI architectural and performance modeling this role you will set the direction for modeling efforts that directly influence our ASIC architecture and microarchitecture (uArch) designs.

You will collaborate closely with system architects chip designers and cross-functional teams to evaluate design trade-offs identify bottlenecks and deliver actionable insights that shape the future of large-scale AI networking. This is an opportunity to establish a modeling strategy at the cutting edge of AI hardware while working alongside a team of talented performance engineers.

Responsibilities

• Participate in the development and deployment of high-level performance models for networking devices to guide architectural decisions.
• Define modeling methodologies and frameworks that ensure consistency accuracy and scalability across projects.
• Partner closely with ASIC architects and uArch teams to evaluate trade-offs in throughput latency power and area.
• Drive performance analysis and bottleneck identification to inform and influence architecture and design choices.
• Oversee the creation and validation of structural and traffic models to explore real-world workloads and system scenarios.

Qualifications

• MSEE/PhD in Electrical Engineering Computer Engineering or a related field with 10 years of relevant industry experience.
• Proven track record of technical leadership in performance modeling or architecture for ASICs SoCs or networking systems.
• Deep expertise in networking protocols such as Ethernet and PCIe.
• Proficiency in modeling languages and tools including C C Python and scripting environments.
• Strong background in FPGA/ASIC design flows including synthesis simulation and verification tools (e.g. Verilog VHDL Synopsys Cadence).
• Demonstrated ability to drive architectural discussions and influence design trade-offs through modeling insights.