Sr Principal Design Engineer (Chiplet Solutions)

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software hardware and IP that turn design concepts into reality.

Cadence customers are the worlds most innovative companies delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer hyperscale computing 5G communications automotive aerospace industrial and health.

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title:Sr Principal Design Engineer

Location: Edinburgh United Kingdom

Reports to:Design Engineering Group Director

Job Overview:

The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) and Chiplet Solutions for a variety of High-Tech Markets. The Cadence IP & Chiplet solutions allow our Customers to tackle Silicon product development in a system context enabling them to focus on product differentiation and to reduce time to volume.

The Cadence Vision is to deliver industry leading IP & Chiplet solutions to enable our customers to be successful across fast-moving application spaces such as Physical AI DataCentre and High Performance Computing.

The Sr Principal Design Engineer will be based in Edinburgh as part of an experienced Front-End Engineering Team working with our Global Chiplet team in Europe India and the USA.

Job Responsibilities:

• Technical leadership of complex Silicon programs consisting of leading-edge IP
• Work closely with our Chiplet Architecture team to define next generation Chiplets
• Integration of Cadence IP Solutions e.g. UCIe PCIe Ethernet USB NPU Audio Vision
• Integration of partner IP Solutions e.g. CPUs ISP Silicon Monitors NoCs
• Hands-on leadership of RTL Testbench Formal Analysis and Trial Synthesis activities
• Quality Assurance via implementation of hierarchical LINT CDC and release flows
• Planning of activities and milestones for Chiplet Subsystems and System IP development
• Leadership of cross-functional technical meetings with domain leads e.g. Verification SW
• Support customer pre-sales and post-sales meetings
• Participate in Technical Review Meetings and Checklist Reviews as part of ISO-9001
• Represent Cadence by presenting at Industry Conferences such as IEEE DAC CDNLive

Job Qualifications:

• Degree in Electrical/Electronic Engineering Microelectronics or a related discipline
• 12 years experience in microelectronics/EDA industry
• Experience of Verilog RTL Design essential
• Experience of Metric Driven Verification (MDV) essential
• Experience of Front-end design tools covering LINT Synthesis CDC Analysis essential
• Experience of SoC Architecture and Development essential
• Experience of Technical Team leadership essential
• Excellent oral and written English essential
• Self-motivated with excellent planning interpersonal and communication skills

Additional Skills/Preferences:

• Experience of AMBA PCIe CXL & UCIe protocols preferred
• Experience of Quality processes such as ISO-9001 & ISO-26262 preferred

Additional Information:

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

Travel: <10%

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