Lead Design Verification Engineer, High Speed Interface Protocols

Our partner is looking for a Lead Design Verification Engineer to lead functional verification of high speed interface protocol blocks at IP and subsystem level.

The role combines hands on verification ownership with technical leadership covering UVM environments protocol compliance debug coverage closure and coordination with RTL architecture firmware and verification teams.

Location: Barcelona Spain Hybrid
Level: Lead

• Lead IP and subsystem level functional verification

• Architect and maintain UVM verification environments

• Own verification of PCIe UCIe SerDes and related interfaces

• Act as protocol expert for AXI CXS AHB CHI and other bus protocols

• Debug RTL DV model and specification mismatches

• Drive coverage closure and sign off

• Triage simulation failures and drive bug resolution

• Optimize simulation runtime and compile flows

• Develop scripts and verification automation

• Guide and support verification engineers

• Maintain verification methodology and technical documentation

• 10 years of ASIC or SoC verification experience

• Recent high speed protocol verification experience

• Strong PCIe UCIe or SerDes knowledge

• Deep AXI CXS AHB or CHI expertise

• Strong SystemVerilog and UVM

• Coverage driven verification and sign off

• Strong SoC and digital design knowledge

• VCS Xcelium or Questa

• Excellent debugging and problem solving skills

• Bachelor or Master degree in Electrical Engineering Computer Engineering or related field

• RISC V experience

• AI assisted verification tools

• Python Perl or Tcl

• Git or Perforce

• LSF or Grid Engine

• Strong technical documentation and communication skills

• Flexible working hours

• Hybrid model 4 days office 1 day from home

• 1 week per year working from anywhere

• 25 days annual leave plus December 24 and 31

• Monthly food allowance

• Private medical insurance

• Relocation bonus

• Housing search support

• Visa support if required

• Family relocation support

• Virtual shares

• Language classes

• Tax incentive subject to eligibility