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Embedded Engineer
Job Location:
Monthly Salary:
Posted:
16 September 2026 (8 hours ago)
Posted:
Application Deadline:
14 December 2026
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Senior Embedded Engineer
We are looking for a highly experienced Senior Embedded Engineer to join our partners engineering team and play a key role in the architecture development and production of high-volume cost-sensitive microelectronic products.
Key Responsibilities:
- Collaborate closely with Electrical Engineering teams to define product requirements system specifications and ASIC/SoC architectures for high-volume cost-constrained microelectronic applications.
- Evaluate system-level architectural options and drive technical trade-offs between performance power die size cost manufacturability yield and time-to-market.
- Lead the technical evaluation selection and integration of third-party semiconductor IP including analog compute memory connectivity and other relevant IP blocks.
- Represent the engineering organization in technical discussions with foundries OSATs semiconductor IP providers and manufacturing partners.
- Support technology roadmap discussions and proactively identify manufacturing technology and supply-chain risks.
- Provide technical input into process-node and PDK selection considering performance requirements power consumption cost yield foundry maturity and production readiness.
- Drive Design-for-Cost (DfC) Design-for-Manufacturing (DfM) Design-for-Assembly (DfA) and Design-for-Yield (DfY) principles from architecture through production.
- Guide decisions related to floorplanning die size pin count pin placement package selection and assembly strategy optimizing both technical and commercial outcomes.
- Develop and contribute to semiconductor cost models covering wafer economics packaging OSAT costs testing yield logistics and other unit-cost drivers.
- Work closely with test and validation teams to define production-test strategies that maximize fault coverage while minimizing test time and cost.
- Analyze silicon test results production data and yield metrics to identify opportunities for design manufacturing and cost optimization.
- Support root-cause analysis of silicon manufacturing and yield issues and drive corrective actions with internal and external stakeholders.
- Incorporate supply-chain resilience and multi-sourcing considerations into architectural and technology decisions.
- Evaluate the impact of die size process-node selection foundry maturity packaging and manufacturing choices on sourcing flexibility and supply-chain risk.
- Collaborate with cross-functional teams throughout the complete ASIC/SoC lifecycle from architecture and technology selection to design tape-out silicon bring-up validation production and yield optimization.
- Contribute to continuous improvement of semiconductor design and manufacturing processes with a strong focus on scalability and high-volume production.
- Travel internationally as required including regular travel to Denmark several times per month as well as periodic travel to Boston Europe and Asia depending on project requirements and candidate location.
Required Qualifications & Technical Expertise:
- 8 years of relevant experience in ASIC microarchitecture ASIC design SoC design embedded semiconductor development or a closely related electrical engineering discipline.
- Demonstrated track record of successfully taking ASIC/SoC products through the complete development lifecycle including multiple successful tape-outs.
- Strong understanding of ASIC/SoC architecture and microarchitecture with the ability to evaluate complex system-level trade-offs and make sound architectural decisions.
- Hands-on experience evaluating selecting and integrating third-party semiconductor IP.
- Strong understanding of how IP selection and integration decisions influence overall system architecture performance cost and risk.
- Good knowledge of semiconductor foundry processes process nodes and PDKs including their impact on power performance cost yield and production readiness.
- Practical experience with advanced semiconductor packaging and assembly strategies including their impact on performance cost manufacturing and supply-chain considerations.
- Strong understanding of semiconductor testing methodologies including test strategies fault coverage test time and production-test cost optimization.
- Solid understanding of semiconductor yield fundamentals including die-size/yield relationships production-line yield analysis silicon test data and yield improvement.
- Practical experience applying DfC DfM DfA and DfY principles to semiconductor products.
- Good understanding of wafer economics OSAT operations packaging costs test costs and semiconductor unit-cost drivers.
