ASIC Engineering Director

Application close date:

Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin we envision millions of people living and working in space for the benefit of Earth. Were working to develop reusable safe and low-cost space vehicles and systems within a culture of safety collaboration and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!

Blue Origin is pioneering the future of space-based communications with TeraWave a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO) providing enterprise-grade connectivity for critical operations worldwide.

Blue Origin is seeking an experienced ASIC Engineering Director & Site Leader to establish and lead the ASIC engineering organization in Krakow Poland. The Krakow team will have a strong emphasis on design verification while also developing capabilities in front-end design digital architecture and implementation embedded hardware integration and selected digital-top mixed-signal functions. The Krakow organization will contribute to the development of complex communication systems and high-performance SoCs for TeraWave supporting Blue Origins mission of enabling millions of people to live and work in space for the benefit of Earth. The successful candidate will combine deep technical expertise in ASIC and communication SoC development with demonstrated experience building high-performing teams establishing effective engineering processes and delivering complex silicon addition to leading the ASIC organization this person will serve as the Krakow engineering site leader and will have responsibility for the sites shared ASIC and prototype integration laboratory. Lab execution will be supported through technical leads in design verification software firmware and RF/mixed-signal engineering. The lab will support FPGA prototyping hardware-in-the-loop testing embedded software and firmware integration modem and digital beamformer development and system-level debug. This role will partner closely with ASIC systems software firmware analog/mixed-signal RF physical design DFT product engineering and program leadership teams across Blue Origin. While this position is not expected to directly manage the analog/mixed-signal organization prior experience with communication SoCs and digital-top mixed-signal design integration and verification will be highly valuable.

Responsibilities:

Establish lead and grow the Krakow ASIC engineering organization initially with a strong focus on design verification and expanding into front-end design digital architecture and related digital functions.

Define and execute the organizations technical strategy staffing plan operating model engineering processes and development roadmap.

Recruit develop mentor and retain engineering managers technical leads staff engineers and individual contributors.

Build a culture of technical excellence ownership collaboration accountability and continuous improvement.

Lead ASIC development across the product lifecycle from requirements and architecture through RTL design verification implementation tape-out silicon bring-up and product qualification.

Own the Krakow teams execution against program commitments including scope schedule quality staffing resource planning and risk management.

Establish scalable ASIC verification methodologies and infrastructure for block- subsystem- and SoC-level verification.

Ensure disciplined verification planning and closure including requirements traceability test planning functional and code coverage assertions formal verification emulation FPGA prototyping gate-level simulation software simulation and regression management.

Build strong collaboration between design and verification teams to improve design quality reduce integration risk and accelerate issue discovery and closure.

Support the development of digital front-end capabilities including RTL design microarchitecture CDC/RDC lint clocking low-power and multi-voltage design interface integration and design quality.

Provide technical oversight for integration of complex digital and communication SoCs including processors bus fabrics DMA NoCs memory controllers highspeed interfaces external IP and analog/mixed-signal macros.

Guide development and verification of DSP-intensive communication systems including modem architectures coding and framing PHY and MAC functions FIR filters CORDIC FFT/IFFT MAC engines circular buffers and time-bound data movement.

Promote the use of golden reference models and cross-domain verification using MATLAB System C C/C Python and System Verilog.

Ensure robust verification of digital-top mixed-signal systems through appropriate behavioral models co-simulation analog macro abstraction and system-level validation.

Partner with analog/mixed-signal and RF leaders to establish effective specifications interfaces models integration plans and verification strategies.

Support implementation DFT LEC floorplanning static timing analysis power analysis physical verification and signoff activities.

Establish effective flows between ASIC and FPGA implementations emulation prototyping pre-silicon verification and post-silicon validation.

Partner with software and firmware teams on hardware/software co-simulation processor integration boot flows drivers diagnostics and system-level validation.

Participate in silicon bring-up characterization failure analysis root-cause investigation and corrective action following tape-out.

Lead technical reviews architecture assessments design reviews verification reviews and lessons-learned activities.

Serve as the accountable engineering leader for the Krakow ASIC and prototype integration lab with execution delegated through technical leads for design verification software firmware and RF/mixed-signal engineering.

Ensure that shared lab infrastructure effectively supports FPGA prototyping hardware-in-the-loop testing embedded software and firmware integration modem and digital beamformer development and system-level debug.

Establish appropriate processes for lab planning equipment configuration prototype tracking test automation data management maintenance calibration safety and infrastructure reliability.

Partner with facilities IT security procurement and EHS teams on lab operations equipment procurement physical infrastructure access controls and safe operation.

Manage lab capacity and capital planning in alignment with program priorities and organizational growth.

Develop strong working relationships with engineering leaders and stakeholders in Krakow and across Blue Origins global organization.

Represent the Krakow ASIC organization in program reviews planning activities technical forums and executive discussions.

Establish a collaborative inclusive and high-performing Krakow engineering site culture in partnership with other functional leaders.

Support local site operations workforce planning employee development engineering communications and cross-functional coordination.

Travel as required to support collaboration with other Blue Origin locations suppliers technology partners and program teams.

Minimum Qualifications:

Bachelors degree in Electrical Engineering Computer Engineering Computer Science or a related technical discipline.

15 years of relevant experience in ASIC SoC semiconductor or complex digital system development.

8 years of experience leading engineering organizations including responsibility for hiring team development execution and technical direction.

Demonstrated experience leading the development and delivery of complex ASICs or SoCs through tape-out and silicon bring-up.

Significant experience with design verification of complex SoCs using System Verilog and modern verification methodologies.

Strong understanding of verification planning and closure including functional coverage code coverage assertions formal verification regressions emulation FPGA prototyping gate-level simulation and software co-simulation.

Experience leading teams responsible for block- subsystem- and full-SoC verification.

Strong understanding of digital front-end design and ASIC implementation flows including RTL design CDC/RDC lint timing constraints clocking low-power or multi-voltage design DFT LEC floorplanning static timing analysis and power analysis.

Experience integrating complex SoC components such as processors cache and memory subsystems MMUs interrupt controllers secure boot bus fabrics AXI DMA NoCs and external IP.

Experience with high-speed and system interfaces such as DDR PCIe Ethernet SPI and high-speed SerDes.

Experience with DSP-intensive systems and/or modern communication SoCs including modem PHY MAC coding framing and high-throughput data movement.

Demonstrated ability to define requirements specifications development plans verification plans schedules and technical milestones.

Experience building or operating a hardware ASIC FPGA embedded systems RF or system-integration laboratory.

Experience with hardware-in-the-loop testing FPGA prototyping lab automation or automated hardware regression infrastructure.

Demonstrated ability to lead through functional technical leads across multiple engineering disciplines.

Strong technical judgment and the ability to balance performance power area schedule quality cost and risk.

Excellent written verbal and interpersonal communication skills.

Demonstrated ability to lead through influence across geographically distributed and cross-functional teams.

Ability to work onsite in Krakow Poland.

Preferred Qualifications:

MS or PhD in Electrical Engineering Computer Engineering Computer Science or a related technical discipline.

Experience building a new ASIC or semiconductor engineering organization or establishing a new engineering site.

Experience leading organizations spanning design verification RTL/front-end design digital architecture emulation FPGA prototyping and post-silicon validation.

Deep experience with communication SoCs modem architectures wireless or satellite communications RF systems or other DSP-intensive products.

Experience with DSP architectures including FIR CORDIC FFT/IFFT MAC channelization sample-rate conversion circular buffers and analog-to-digital interfaces.

Experience with deterministic latency time-slotted systems timestamping and real-time data processing.

Experience developing reusable verification environments and portable verification flows across simulation emulation FPGA pre-silicon and silicon environments.

Experience integrating software build flows with simulation FPGA emulation and verification environments.

Experience qualifying FPGA prototypes or emulation platforms and partitioning verification across simulation emulation and prototyping.

Experience with digital-top mixed-signal SoCs including analog macro modeling AMS co-simulation mixed-mode verification and top-level integration.

Familiarity with analog/mixed-signal design and verification flows and tools such as Cadence Virtuoso Spectre AMS MATLAB and SystemVerilog-AMS.

Experience collaborating with analog RF PLL data converter power management and other mixed-signal design teams.

Experience with silicon characterization post-silicon debug production test and yield improvement.

Experience managing external IP vendors design partners EDA providers foundries and technology partners.

Experience establishing shared engineering lab processes including equipment procurement asset tracking configuration management calibration maintenance and safety.

Experience with lab automation using Python SCPI MATLAB LabVIEW or comparable tools.

Experience supporting conducted RF link closure modem validation digital beamformer testing or communications-system integration.

Demonstrated experience developing engineering managers and senior technical leaders.

Experience working in a highly regulated safety-critical aerospace defense communications or other high-reliability environment.

Fluency in Polish or experience working effectively within Polish engineering organizations.

Culture Statement

Dont meet all desired requirements Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At Blue Origin we are dedicated to building an authentic workplace so if youre excited about this role but your past experience doesnt align perfectly with every desired qualification in the job description we encourage you to apply anyway. You may be just the right candidate for this or other roles.

Candidates may be subject to verification and BGS screening as per applicable law.